38C5 Group (One Time PROM version) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 38C5 group is the 8-bit microcomputer based on the 740 family core technology. The 38C5 group has an LCD drive control circuit, an A/D converter, and a serial interface as additional functions. The various microcomputers in the 38C5 group include variations of internal memory type, memory size, and packaging. This data sheet has described only the One Time PROM version of 38C5 group. Refer to "38C5 Group Datasheet" about products other than the One Time PROM version. FEATURES Basic machine-language instructions ....................................... 71 The minimum instruction execution time .......................... 0.67 s (at 6 MHz oscillation frequency) Memory size ROM ............................................................................ 60 K bytes RAM ............................................................................ 2048 bytes Programmable input/output ports ......... 59 (common to SEG: 32) Interrupts ................................................... 17 sources, 16 vectors (Key input interrupt included) Timers ............................................................ 8-bit 4, 16-bit 2 Serial interface Serial I/O1 ...................... 8-bit 1 (UART or Clock-synchronized) Serial I/O2 ..................................... 8-bit 1 (Clock-synchronized) PWM .................. 10-bit 2, 16-bit 1 (common to IGBT output) A/D converter ................................................. 10-bit 8 channels (A/D converter can be operated in low-speed mode.) Watchdog timer ............................................................... 8-bit 1 Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 1 of 75 REJ03B0098-0200 Rev.2.00 Nov 23, 2005 LED direct drive port .................................................................. 6 (average current: 15 mA, peak current: 30 mA, total current: 90 mA) LCD drive control circuit Bias ................................................................................... 1/2, 1/3 Duty ......................................................... Static, 1/2, 1/3, 1/4, 1/8 Common output ....................................................................... 4/8 Segment output ................................................................... 32/36 Main clock generating circuit ...................................................... 1 (connect to external ceramic resonator or on-chip oscillator) Sub-clock generating circuit ........................................................ 1 (connect to external quartz-crystal oscillator) Power source voltage In high-speed mode (f(XIN) = 6 MHz) ......................... 3.0 to 3.6 V In high-speed mode (f(XIN) = 4 MHz) ......................... 2.0 to 3.6 V In middle-speedmode (f(XIN) = 6 MHz) ....................... 1.8 to 3.6 V In low-speed mode ..................................................... 1.8 to 3.6 V Power dissipation (Mask ROM version) * In high-speed mode ................................................. Typ. 15 mW (VCC = 2.5 V, f(XIN) = 4 MHz, Ta = 25C) * In low-speed mode ................................................... Typ. 18 W (VCC = 2.5 V, f(XIN) = stop, f(XCIN) = 32 kHz, Ta = 25C) Operating temperature range ................................... - 20 to 85C APPLICATION Household products, Consumer electronics, etc. PIN CONFIGURATION (TOP VIEW) P20/SEG0/(KW4) P21/SEG1/(KW5) P22/SEG2/(KW6) P23/SEG3/(KW7) P24/SEG4 P25/SEG5 P26/SEG6 P27/SEG7 P00/SEG8 P01/SEG9 P02/SEG10 P03/SEG11 P04/SEG12 P05/SEG13 P06/SEG14 P07/SEG15 P10/SEG16 P11/SEG17 P12/SEG18 P13/SEG19 P14/SEG20 P15/SEG21 P16/SEG22 P17/SEG23 38C5 Group (One Time PROM version) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P47/SRDY2/(KW3) P46/SCLK2/(KW2) P45/SOUT2/(KW1) P44/SIN2/(KW0) P43/SRDY1 P42/SCLK1 P41/TXD P40/RXD AVss VREF P57/AN7/ADKEY0 P56/AN6 P55/AN5 P54/AN4 P53/AN3 P52/AN2 65 40 39 38 37 66 67 68 69 70 71 72 73 74 75 76 77 M38C59GFFP 78 79 80 P51/AN1/RTP1 P50/AN0/RTP0 P67/CNTR1/(LED5) P66/INT10/CNTR0/(LED4) P65/TXOUT1 /(LED3) P64/INT2 /(LED2) P63/TXOUT2/(LED1) P62/INT00 /(LED0) CNVSS RESET P61/XCOUT P60/XCIN VSS XIN XOUT VCC P74/PWM1/T4OUT P73/PWM0/T3OUT P72/T2OUT/CKOUT VL3 VL 2 P71/C2/INT11 P70/C1/INT01 VL1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Package type : PLQP0080GA-A (80P6U-A) Fig. 1 M38C59GFFP pin configuration Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 2 of 75 36 35 34 33 32 31 30 29 28 27 26 25 P30/SEG24 P31/SEG25 P32/SEG26 P33/SEG27 P34/SEG28 P35/SEG29 P36/SEG30 P37/SEG31 COM7/SEG32 COM6/SEG33 COM5/SEG34 COM4/SEG35 COM3 COM2 COM1 COM0 38C5 Group (One Time PROM version) 42 41 44 43 52 51 50 49 48 47 46 45 54 53 40 39 38 37 36 35 34 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 33 32 31 30 29 28 27 26 25 24 23 22 M38C59GFHP 21 19 20 18 17 15 16 12 13 14 10 11 8 9 7 4 5 6 3 P67/CNTR1/(LED5) P66/INT10/CNTR0 /(LED4) P65/TXOUT1 /(LED3) P64/INT2 /(LED2) P63/TXOUT2/(LED1) P62/INT00/(LED0) CNVSS RESET P61/XCOUT P60/XCIN VSS XIN XOUT VCC P74/PWM1/T4OUT P73/PWM0/T3OUT P72/T2OUT/CKOUT VL3 VL2 P71/C2/INT11 2 80 1 P21/SEG1/(KW5) P20/SEG0/(KW4) P47/SRDY2/(KW3) P46/SCLK2/(KW2) P45/SOUT2/(KW1) P44/SIN2/(KW0) P43/SRDY1 P42/SCLK1 P41/TXD P40/RXD AVss VREF P57/AN7/ADKEY0 P56/AN10 P55/AN5 P54/AN4 P53/AN3 P52/AN2 P51/AN1/RTP1 P50/AN0/RTP0 55 60 59 58 57 56 P22/SEG2/(KW6) P23/SEG3/(KW7) P24/SEG4 P25/SEG5 P26/SEG6 P27/SEG7 P00/SEG8 P01/SEG9 P02/SEG10 P03/SEG11 P04/SEG12 P05/SEG13 P06/SEG14 P07/SEG15 P10/SEG16 P11/SEG17 P12/SEG18 P13/SEG19 P14/SEG20 P15/SEG21 PIN CONFIGURATION (TOP VIEW) Package type : PLQP0080KB-A (80P6Q-A) Fig. 2 M38C59GFHP pin configuration Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 3 of 75 P16/SEG22 P17/SEG23 P30/SEG24 P31/SEG25 P32/SEG26 P33/SEG27 P34/SEG28 P35/SEG29 P36/SEG30 P37/SEG31 COM7/SEG32 COM6/SEG33 COM5/SEG34 COM4/SEG35 COM3 COM2 COM1 COM0 VL1 P70/C1/INT01 Rev.2.00 Nov 23, 2005 REJ03B0098-0200 Fig. 3 Functional block diagram page 4 of 75 8 Port P4 (8) Port P0 (8) 8 8 Port P5 (8) 4 COM 36 SEG 8 COM 32 SEG or LCD drive control circuit (Clock synchronous) Serial I/O2 (UART or Clock synchronous) Serial I/O1 Serial I/O 10-bit 8-channel A/D conversion 8 Timer Port P6 (8) CPU core 3 2 Port P7 (5) Watchdog timer PWM1 (10 bits) Timer 4 (8 bits) PWM0 (10 bits) Timer 3 (8 bits) Timer 2 (8 bits) Timer 1 (8 bits) RAM (36 bytes) RAM for LCD display ROM Memory (Sub-clock) XCIN-XCOUT IGBT output XIN-XOUT System clock generation (Main clock) On-chip oscillator PWM (16 bits) Timer Y (16 bits) 8 8 Port P3 (8) Timer X (16 bits) Port P2 (8) Internal peripheral function Port P1 (8) 8 FUNCTIONAL BLOCK DIAGRAM 38C5 Group (One Time PROM version) 38C5 Group (One Time PROM version) PIN DESCRIPTION Table 1 Pin description (1) Pin Name VCC, VSS RESET XIN Power source Reset input Clock input XOUT Clock output VL1, VL2, VL3 LCD power source Common output COM0 - COM3 COM4/SEG35 - COM7/SEG32 P00/SEG8 - P07/SEG15 Common output Segment output I/O port P0 P10/SEG16 - P17/SEG23 I/O port P1 P20/SEG0/(KW4)- P23/SEG3/(KW7) P24/SEG4 - P27/SEG7 I/O port P2 P30/SEG24 - P37/SEG31 I/O port P3 P40/RxD P41/TxD P42/SCLK1 P43/SRDY1 P44/SIN2/(KW0), P45/SOUT2/(KW1), P46/SCLK2/(KW2), P47/SRDY2/(KW3), I/O port P4 Rev.2.00 Nov 23, 2005 REJ03B0098-0200 Function Function except a port function * Apply power source voltage to VCC, and 0 V to VSS. * Reset input pin for active "L." * Input and output pins for the main clock generating circuit. * Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. When an external clock is used, connect the clock source to XIN, and leave XOUT pin open. * Feedback resistor is built in between XIN pin and XOUT pin. * Input 0 VL1 VL2 VL3 VCC voltage. * Input 0 - VL3 voltage to LCD. * LCD common output pins. * COM2 and COM3 are not used at 1/2 duty ratio. * COM3 is not used at 1/3 duty ratio. * LCD common/segment output pins. * 8-bit I/O port. * CMOS compatible input level. * CMOS 3-state output structure. * I/O direction register allows each pin to be individually programmed as either input or output. * Pull-up control is enabled in a bit unit. * 8-bit I/O port. * CMOS compatible input level. * CMOS 3-state output structure. * I/O direction register allows each 4-bit pin to be programmed as either input or output. * Pull-up control is enabled in 4-bit unit. * Key input interrupt * 8-bit I/O port. input pins * CMOS compatible input level. * CMOS 3-state output structure. * I/O direction register allows each pin to be individually programmed as either input or output. * Pull-up control is enabled in a bit unit. * 8-bit I/O port. * CMOS compatible input level. * CMOS 3-state output structure. * I/O direction register allows each 4-bit pin to be programmed as either input or output. * Pull-up control is enabled in a bit unit. * Serial I/O1 function pins * 8-bit I/O port. * CMOS compatible input level. * CMOS 3-state output structure. * I/O direction register allows each 4-bit pin to be * Serial I/O2 * Key input interrupt programmed as either input or output. function pins input pins * Pull-up control is enabled in a bit unit. page 5 of 75 38C5 Group (One Time PROM version) PIN DESCRIPTION Table 2 Pin description (2) Pin Name I/O port P5 P50/AN0/RTP0, P51/AN1/RTP1 P52/AN2 - P56/AN6 P57/AN7/ADKEY0 I/O port P6 P60/XCIN, P61/XCOUT P62/INT00/(LED0), P63/TXOUT2/ (LED1), P64/INT2/(LED2) P65/TXOUT1/ (LED3) P66/INT10/ CNTR0/(LED4), P67/CNTR1/ (LED5) Input port P7 P70/C1/INT01, P71/C2/INT11 I/O port P7 P72/T2OUT/ CKOUT P73/PWM0/T3OUT, P74/PWM1/T4OUT CNVSS VREF AVSS CNVSS Analog reference voltage Analog power source Rev.2.00 Nov 23, 2005 REJ03B0098-0200 Function * 8-bit I/O port. * CMOS compatible input level. * CMOS 3-state output structure. * I/O direction register allows each pin to be individually programmed as either input or output. * Pull-up control is enabled in a bit unit. * 8-bit I/O port. * CMOS compatible input level. * CMOS 3-state output structure. * I/O direction register allows each pin to be individually programmed as either input or output. * Pull-up control is enabled in a bit unit. * P62 to P67 (6 bits) are enabled to output large current for LED drive. * 2-bit input port. * CMOS input level. Function except a port function * A/D converter input * Real time port function pins pins * ADKEY input pin * Sub clock generating I/O pins (oscillator connected) * External interrupt pin * Timer X output pin * External interrupt pin * Timer X output pin * Timer X, Timer Y output pins * External interrupt pins * External interrupt pins * External capacitor connect pins for a voltage multiplier of LCD. * Timer 2 output pin * Clock output pin * 3-bit I/O port. * CMOS compatible input level. * PWM output pins * CMOS 3-state output structure. * I/O direction register allows each pin to be individually programmed as either input or output. * Pull-up control is enabled. * Connect to VSS. * Reference voltage input pin for A/D converter. * GND input pin for A/D converter. Connect to VSS. page 6 of 75 * Timer 3 output pin * Timer 4 output pin 38C5 Group (One Time PROM version) PART NUMBERING Product M38C5 9 G F FP Package type FP : PLQP0080GA-A package HP : PLQP0080KB-A package ROM/PROM memory size 1 : 4096 bytes 9 : 36864 bytes 2 : 8192 bytes A : 40960 bytes 3 : 12288 bytes B : 45056 bytes 4 : 16384 bytes C : 49152 bytes 5 : 20480 bytes D : 53248 bytes 6 : 24576 bytes E : 57344 bytes 7 : 28672 bytes F : 61440 bytes 8 : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type G : One Time PROM verison RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes Fig. 4 Part numbering Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 7 of 75 38C5 Group (One Time PROM version) GROUP EXPANSION Renesas plans to expand the 38C5 group (One Time PROM version) as follows. Memory Size One Time PROM size ..................................................... 60 K bytes RAM size ........................................................................ 2048 bytes Packages PLQP0080GA-A .......................... 0.5 mm-pitch plastic molded QFP PLQP0080KB-A .......................... 0.8 mm-pitch plastic molded QFP Memory Expansion Plan Mass production M38C59GF ROM size (60k bytes) 56k 48k 40k 32k 28k 24k 20k 16k 12k 8k 4k 192 256 384 512 640 768 896 1,024 1,536 2,048 RAM size (bytes) Fig. 5 Memory expansion plan Currently supported products are listed below. As of November. 2005 Table 3 Support products Part number M38C59GFFP M38C59GFHP Rev.2.00 Nov 23, 2005 REJ03B0098-0200 ROM size (bytes) ROM size for User in ( ) RAM size (bytes) Package 61440 (61310) 2048 PLQP0080GA-A PLQP0080KB-A page 8 of 75 Remarks One Time PROM version 38C5 Group (One Time PROM version) FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) [Stack Pointer (S)] The 38C5 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. The central processing unit (CPU) has six registers. Figure 6 shows the 740 Family CPU register structure. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as arithmetic data transfer, etc., are executed mainly through the accumulator. The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is "0" , the high-order 8 bits becomes "0016". If the stack page selection bit is "1", the high-order 8 bits becomes "0116". The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 7. Table 4 shows the push and pop instructions of accumulator or processor status register. Store registers other than those described in Figure 7 with program when the user needs them during interrupts or subroutine calls. [Program Counter (PC)] [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. b0 b7 A Accumulator b0 b7 X Index register X b0 b7 Y b7 Index register Y b0 S b15 b7 PCH Stack pointer b0 Program counter PCL b7 b0 N V T B D I Z C Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag Fig. 6 740 Family CPU register structure Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 9 of 75 38C5 Group (One Time PROM version) On-going Routine Interrupt request (Note) M (S) Execute JSR Push return address on stack M (S) (PCH) (S) (S) - 1 M (S) (PCL) (S) (S)- 1 (S) M (S) (S) M (S) (S) Subroutine POP return address from stack (S) + 1 (PCL) M (S) (S) (S) + 1 (PCH) M (S) Note: Condition for acceptance of an interrupt request here (S) - 1 Push return address on stack (PCL) (S) - 1 (PS) Push contents of processor status register on stack (S) - 1 Interrupt Service Routine Execute RTS (S) (PCH) Execute RTI (S) (S) + 1 (PS) M (S) (S) (S) + 1 (PCL) M (S) (S) (S) + 1 (PCH) M (S) I Flag is set from "0" to "1" Fetch the jump vector POP contents of processor status register from stack POP return address from stack Interrupt disable flag is "0" and Interrupt enable bit corresponding to each interrupt source is "1" Fig. 7 Register push and pop at interrupt generation and subroutine call Table 4 Push and pop instructions of accumulator or processor status register Push instruction to stack PHA Accumulator PHP Processor status register Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 10 of 75 Pop instruction from stack PLA PLP 38C5 Group (One Time PROM version) [Processor Status Register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. * Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. * Bit 1: Zero flag (Z) The Z flag is set to "1" if the result of an immediate arithmetic operation or a data transfer is "0", and set to "0" if the result is anything other than "0". * Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". * Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. * Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. When the BRK instruction is generated, the B flag is set to "1" automatically. When the other interrupts are generated, the B flag is set to "0", and the processor status register is pushed onto the stack. * Bit 5: Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations. * Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. * Bit 7: Negative flag (N) The N flag is set to "1" if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 5 Set and clear instructions of each bit of processor status register Set instruction Clear instruction Rev.2.00 Nov 23, 2005 REJ03B0098-0200 C flag SEC CLC Z flag - - page 11 of 75 I flag SEI CLI D flag SED CLD B flag - - T flag SET CLT V flag - CLV N flag - - 38C5 Group (One Time PROM version) [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit and the control bit for the internal system clock etc. The CPU mode register is allocated at address 003B16. After system is released from reset, the on-chip oscillator mode is selected, and the XIN-XOUT oscillation and the XCIN-XCOUT oscillation are stopped. b7 When the low-, middle- or high-speed mode is used after the XIN- XOUT oscillation and the XCIN-XCOUT oscillation are enabled, wait in the on-chip oscillator mode etc. until oscillation stabilizes, and then, switch the operation mode. When the middle- and high-speed mode are not used (XIN-XOUT oscillation and external clock input are not performed), connect XIN to VCC through a resistor. b0 CPU mode register (CPUM (CM) : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : Not available 1 1 : Stack page selection bit 0 : 0 page 1 : 1 page Main clock selection bit 0 : XIN input signal (XIN-XOUT oscillating) 1 : On-chip oscillator (internal system clock: only frequency divided by 32 is valid.) Port Xc switch bit 0 : I/O port function (Oscillation stop) 1 : XCIN-XCOUT oscillating function XIN-XOUT oscillation stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit (this bit is invalid when on-chip oscillator is selected.) 0 : f(XIN)/2 (high-speed mode) 1 : f(XIN)/8 (middle-speed mode) Internal system clock selection bit 0 : Main clock selected (middle-/high-speed, on-chip oscillator mode) 1 : XCIN-XCOUT selected (low-speed mode) Fig. 8 Structure of CPU mode register After releasing reset N Start with a on-chip oscillator. Initial value of CPUM is 6816. As for the details of condition for transition among each mode, refer to the state transition of system clock. Low-, middle-, or high-speed mode ? Y Start the oscillation (bits 4 and 5 of CPUM) Wait by on-chip oscillator operation until establishment of oscillator clock System can operate in on-chip oscillator mode until oscillation stabilize. Select internal system clock (bit 3 or bit 7 of CPUM) Select internal system clock. Do not change bit 3 and bit 7, or bit 6 and bit 7 of CPUM at the same time. Switch the main clock division ratio selection bit (bit 6 of CPUM) Select main clock division ratio. Switch to high-speed mode here, if necessary. Main routine Fig. 9 Switch procedure of CPU mode register Rev.2.00 Nov 23, 2005 REJ03B0098-0200 Oscillator starts oscillation. Do not change bit 3, bit 6 and bit 7 of CPUM until oscillation stabilizes. page 12 of 75 38C5 Group (One Time PROM version) MEMORY Special Function Register (SFR) Area Zero Page The Special Function Register area in the zero page contains control registers such as I/O ports and timers. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Access to this area with only 2 bytes is possible in the special page addressing mode. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. 000016 RAM area Zero page 004016 Address XXXX16 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 RAM size (bytes) 192 256 384 512 640 768 896 1024 1536 2048 SFR area RAM 010016 XXXX16 Reserved area 084016 086316 0FF016 100016 LCD display RAM area Not used SFR area YYYY16 ROM ROM area ROM size (bytes) 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 Address YYYY16 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 Fig. 10 Memory map diagram Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 13 of 75 Address ZZZZ16 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 Reserved ROM area (128 bytes) ZZZZ16 FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area Special page 38C5 Group (One Time PROM version) 000016 Port P0 (P0) 000116 Port P0 direction register (P0D) 000216 Port P1 (P1) 000316 Port P1 direction register (P1D) 000416 Port P2 (P2) 000516 Port P2 direction register (P2D) 000616 Port P3 (P3) 000716 Port P3 direction register (P3D) 000816 Port P4 (P4) 000916 Port P4 direction register (P4D) 000A16 Port P5 (P5) 000B16 Port P5 direction register (P5D) 000C16 Port P6 (P6) 000D16 Port P6 direction register (P6D) 000E16 Port P7 (P7) 000F16 Port P7 direction register (P7D) 001016 001116 001216 RRF register (RRFR) 001316 LCD mode register 1 (LM1) 001416 LCD mode register 2 (LM2) 001516 AD control register (ADCON) 001616 AD conversion register (low-order) (ADL) 001716 AD conversion register (high-order) (ADH) 001816 Transmit/receive buffer register 1 (TB1/RB1) 001916 Serial I/O1 status register (SIO1STS) 001A16 Serial I/O1 control register (SIO1CON) 001B16 UART control register (UARTCON) 001C16 Baudrate generator (BRG) 001D16 Serial I/O2 control register (SIO2CON) 001E16 Reserved area (access disabled) 001F16 Serial I/O2 register (SIO2) 0FF016 PULL register 1 (PULL1) 0FF116 PULL register 2 (PULL2) 0FF216 PULL register 3 (PULL3) 0FF316 Clock output control register (CKOUT) 0FF416 Segment output disable register 0 (SEG0) 0FF516 Segment output disable register 1 (SEG1) 0FF616 Segment output disable register 2 (SEG2) 0FF716 Key input control register (KIC) Note. Do not access to the SFR area including nothing. Fig. 11 Memory map of special function register (SFR) Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 14 of 75 002016 Timer 1 (T1) 002116 Timer 2 (T2) 002216 Timer 3 (T3) 002316 Timer 4 (T4) 002416 PWM01 register (PWM01) 002516 Timer 12 mode register (T12M) 002616 Timer 34 mode register (T34M) 002716 Timer 1234 mode register (T1234M) 002816 Timer 1234 frequency division selection register (PRE1234) 002916 Watchdog timer control register (WDTCON) 002A16 Timer X (low-order) (TXL) 002B16 Timer X (high-order) (TXH) 002C16 Timer X (extension) (TXEX) 002D16 Timer X mode register (TXM) 002E16 Timer X control register 1 (TXCON1) 002F16 Timer X control register 2 (TXCON2) 003016 Compare register 1 (low-order) (COMP1L) 003116 Compare register 1 (high-order) (COMP1H) 003216 Compare register 2 (low-order) (COMP2L) 003316 Compare register 2 (high-order) (COMP2H) 003416 Compare register 3 (low-order) (COMP3L) 003516 Compare register 3 (high-order) (COMP3H) 003616 Timer Y (low-order) (TYL) 003716 Timer Y (high-order) (TYH) 003816 Timer Y mode register (TYM) 003916 Timer Y control register (TYCON) 003A16 Interrupt edge selection register (INTEDGE) 003B16 CPU mode register (CPUM) 003C16 Interrupt request register 1 (IREQ1) 003D16 Interrupt request register 2 (IREQ2) 003E16 Interrupt control register 1 (ICON1) 003F16 Interrupt control register 2 (ICON2) 0FF816 0FF916 0FFA16 0FFB16 0FFC16 0FFD16 0FFE16 0FFF16 38C5 Group (One Time PROM version) I/O PORTS Direction Registers (Ports P0-P6, P72-P74) The I/O ports P0-P6, P72-P74 have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When "0" is written to the bit of the direction register, the corresponding pin becomes an input pin. As for ports P0-P3, when "1" is written to the bit of the direction register and the segment output disable register, the corresponding pin becomes an output pin. As for ports P4-P6, P72-P74, when "1" is written to the bit of the direction register, the corresponding pin becomes an output pin. If data is read from a pin set to output, the value of the port latch is read, not the value of the pin itself. However, when RTP1, RTP0, TXOUT1, TXOUT2, T4OUT, T3OUT and T2OUT/CKOUT output are selected, the output value is read, not the value of the port latch. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Ports P70, P71 b7 b0 P50 pull-up P51 pull-up P52 pull-up P53 pull-up P54 pull-up P55 pull-up P56 pull-up P57 pull-up b7 b0 b7 b0 b7 Direction register "0" "1" "0" Input port No pull-up Input port Pull-up "1" Segment output Port output b0 0: No pull-up 1: Pull-up Segment output disable register 1 (SEG1 : address 0FF516) P20 pull-up P21 pull-up P22 pull-up P23 pull-up P24 pull-up P25 pull-up P26 pull-up P27 pull-up Initial state b7 Fig. 12 Structure of ports P0 to P3 b0 0: No pull-up 1: Pull-up Segment output disable register 0 (SEG0 : address 0FF416) P00 pull-up P01 pull-up P02 pull-up P03 pull-up P04 pull-up P05 pull-up P06 pull-up P07 pull-up b7 Segment output disable register b0 0: No pull-up 1: Pull-up PULL register 3 (PULL3 : address 0FF216) P40-P43 pull-up P44-P47 pull-up P72-P74 pull-up Not used (return "0 " when read) (Do not write to "1 ") Pull-up Control 0: No pull-up 1: Pull-up PULL register 2 (PULL2 : address 0FF116) P60 pull-up P61 pull-up P62 pull-up P63 pull-up P64 pull-up P65 pull-up P66 pull-up P67 pull-up These are input ports which are shared with the voltage multiplier. When these are read out at using the voltage multiplier, the contents are "1". Each individual bit of ports P0-P3 can be pulled up with a program by setting direction registers and segment output disable registers 0 to 2 (addresses 0FF416 to 0FF616). The pin is pulled up by setting "0" to the direction register and "1" to the segment output disable register. By setting the PULL registers (addresses 0FF016 to 0FE216), ports P4-P7 can control pull-up with a program. However, the contents of PULL register do not affect ports programmed as the output ports. PULL register 1 (PULL1 : address 0FF016) 0: No pull-up 1: Pull-up Segment output disable register 2 (SEG2 : address 0FF616) P10-P13 pull-up P14-P17 pull-up P30-P33 pull-up 0: No pull-up P34-P37 pull-up 1: Pull-up Not used (return "0 " when read) (Do not write to "1 ") Note: The PULL register and segment output disable register affect only ports programmed as the input ports. Fig. 13 Structure of PULL register and segment output disable register Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 15 of 75 38C5 Group (One Time PROM version) Table 6 List of I/O port function Pin P00/SEG8 - P07/SEG15 P10/SEG16 - P17/SEG23 P20/SEG0/(KW4)- P23/SEG3/(KW7) P24/SEG4 - P27/SEG7 P30/SEG24 - P37/SEG31 P40/RxD P41/TxD P42/SCLK1 P43/SRDY1 P44/SIN2/(KW0), P45/SOUT2/(KW1), P46/SCLK2/(KW2), P47/SRDY2/(KW3) P50/AN0/RTP0, P51/AN1/RTP1 P52/AN2 - P56/AN6 P57/AN7/ADKEY0 P60/XCIN, P61/XCOUT P62/INT00/(LED0) Name Port P0 Port P1 Port P2 Port P3 Port P4 Input/Output Input/Output, individual bits Input/Output, individual bits Input/Output, individual bits I/O format Non-port function CMOS compatible input level LCD segment CMOS 3-state output output CMOS compatible input level CMOS 3-state output CMOS compatible input level Key input CMOS 3-state output (key-on wakeup) interrupt input Input/Output, individual bits Input/Output, individual bits CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output Port P5 Input/Output, CMOS compatible input level individual bits CMOS 3-state output Port P6 Input/Output, CMOS compatible input level individual bits CMOS 3-state output Port P7 Input P63/TXOUT2/ (LED1) P64/INT2/(LED2) P65/TXOUT1/ (LED3) P66/INT10/ CNTR0/(LED4), P67/CNTR1/ (LED5) P70/C1/INT01, P71/C2/INT11 Input/Output, CMOS compatible input level individual bits CMOS 3-state output P72/T2OUT/CKOUT P73/PWM0/T3OUT, P74/PWM1/T4OUT COM0-COM3 COM4/SEG35- COM7/SEG32 CMOS compatible input level Common Output Common/ Segment Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 16 of 75 LCD common output LCD common/segment output Related SFRs Ref. No. Segment output disable (1) register 0 Segment output disable register 2 Segment output disable (2) register 1 Key input control register Segment output disable (1) register 1 Segment output disable register 2 PULL register 3 (3) Serial I/O1 function I/O Serial I/O1 control register (4) Serial I/O1 status register (5) UART control register (6) Key input PULL register 3 (7) Serial I/O2 (key-on wakeup) Serial I/O2 control register (8) function I/O interrupt input Serial I/O2 register (9) Key input control register (10) PULL register 1 (11) A/D conversion Real time port function A/D control register input output Timer Y mode register PULL register 1 (12) A/D control register ADKEY input (13) PULL register 2 (14) Sub-clock oscillation circuit CPU mode register (15) PULL register 2 (16) External interrupt input Interrupt edge selection register PULL register 2 (18) Timer X output 2 Timer X mode register Timer X control registers 1, 2 PULL register 2 (17) External interrupt input Interrupt edge selection register PULL register 2 (18) Timer X output 1 Timer X mode register Timer X control register 1 PULL register 2 (19) Timer X function input Interrupt edge selection External interrupt input register Timer X mode register Timer X control registers 1, 2 PULL register 2 (17) Timer Y function input Timer Y mode register Interrupt edge selection (20) External interrupt input LCD voltage multiplier input register LCD mode registers 1, 2 (21) Timer 2 output Clock output PULL register 3 Timer 3 output PWM output Timer 1234 mode register Timer 1234 frequency Timer 4 output division register LCD mode registers 1, 2 (22) LCD common output LCD segment (23) output 38C5 Group (One Time PROM version) (2)Ports P20-P23 (1)Ports P0,P1,P24-P27,P3 VL3/VL2 VL3/VL2 Segment data Segment data VL1/VSS VL1/VSS Segment output disable bit Segment output disable bit Direction register Direction register Data bus Port latch Data bus Port latch Key-on wakeup interrupt input (3)Port P40 (4)Port P41 Pull-up control Serial I/O1 enable bit Receive enable bit Data bus Pull-up control P41/TxD P-channel output disable bit Serial I/O1 enable bit Transmit enable bit Direction register Direction register Port latch Data bus Serial I/O input Port latch Serial I/O output (5)Port P42 (6)Port P43 Serial I/O1 synchronous clock selection bit Pull-up control Serial I/O1 enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register Data bus Data bus Key input control Port latch Port latch Serial I/O1 ready output Serial I/O1 clock output Serial I/O1 clock input Fig. 14 Port block diagram (1) Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 17 of 75 Pull-up control 38C5 Group (One Time PROM version) (8)Port P45 (7)Port P44 Pull-up control P45/SOUT2 P-channel output disable bit Direction register Direction register Port latch Data bus Data bus Port latch Serial I/O2 output Serial I/O2 input Key input control Key-on wakeup interrupt input (9)Port P46 Key input control Key-on wakeup interrupt input (10)Port P47 Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Pull-up control Pull-up control SRDY2 output selection bit Direction register Direction register Data bus Pull-up control Serial I/O2 transmit end signal Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Data bus Port latch Port latch Serial I/O2 ready output Serial I/O2 clock output Serial I/O2 clock input Key input control Key-on wakeup interrupt input (11)Ports P50,P51 Key input control Key-on wakeup interrupt input (12)Ports P52-P56 Pull-up control Pull-up control Direction register Direction register Data bus Port latch Data bus Port latch Real time port control bit Data for real time port ADKEY enable bit Analog input pin selection bit A/D conversion input Fig. 15 Port block diagram (2) Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 18 of 75 ADKEY enable bit Analog input pin selection bit A/D conversion input 38C5 Group (One Time PROM version) (14) Port P60 (13) Port P57 Pull-up control Port Xc switch bit Pull-up control Port Xc switch bit Direction register Direction register Data bus Data bus Port latch Port latch Sub-clock oscillation circuit input ADKEY selection bit ADKEY enable bit Analog input pin selection bit A/D conversion input (15) Port P61 Pull-up control (16) Port P62 Pull-up control Port Xc switch bit Port Xc switch bit Direction register Data bus Direction register Data bus Port latch Port latch Sub-clock oscillation circuit Port P60 INT0 interrupt input INT0 input port switch bit Xc oscillation enable (18) Ports P63,P65 (17) Ports P64,P67 Pull-up control Pull-up control Direction register Direction register Data bus Data bus Port latch Port latch CNTR1 interrupt input INT2 interrupt input Fig. 16 Port block diagram (3) Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 19 of 75 Pulse output mode Timer X output 1 Timer X output 2 38C5 Group (One Time PROM version) (19) Port P66 (20) Ports P70, P71 Pull-up control Direction register Data bus Port latch Data bus Voltage multiplier control bit C1,C2 INT0 interrupt INT1 interrup INT0 input port switch bit INT1 input port switch bit CNTR0 interrupt input INT1 interrupt input INT1 input port switch bit (22) COM0 to COM3 (21) PortsP72,P73,P74 Pull-up control VL3 Direction register VL2 Data bus Port/Timer output selected VSS Timer output/PWM output Timer output/system clock output/XCIN output (23) COM4/SEG35 to COM7/SEG32 VL3 VL2 VL1 The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value. VL2/VL3 Duty ratio selection bits VSS Segment data VL1/VSS Fig. 17 Port block diagram (4) Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 20 of 75 The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value. VL1 Port latch 38C5 Group (One Time PROM version) Termination of unused pins * Termination of common pins I/O ports: Select an input port or an output port and follow each processing method. Output ports: Open. Input ports: If the input level become unstable, through current flow to an input circuit, and the power supply current may increase. Especially, when expecting low consumption current (at STP or WIT instruction execution etc.), pull-up or pull-down input ports to prevent through current (builtin resistor can be used). We recommend processing unused pins through a resistor which can secure IOH(avg) or IOL(avg). Because, when an I/O port or a pin which have an output function is selected as an input port, it may operate as an output port by incorrect operation etc. Table 7 Termination of unused pins Pin P00/SEG8-P07/SEG15 P10/SEG16-P17/SEG23 P20/SEG0-P27/SEG7 P30/SEG24-P37/SEG31 P40/RxD Termination 1 (recommend) I/O port When selecting RxD function, perform termination of input port. When selecting TxD function, perform termination of input port. When selecting external clock input, perform termination of output port. When selecting SRDY1 function, perform termination of output port. When selecting SIN2 function, perform termination of input port. When selecting SOUT2 function, perform termination of output port. When selecting external clock input, perform termination of output port. When selecting SRDY2 function, perform termination of output port. When selecting AN function, these pins can be opened. (A/D conversion result cannot be guaranteed.) P42/SCLK1 P43/SRDY1 P44/SIN2 P45/SOUT2 P46/SCLK2 P47/SRDY2 P50/AN0/RTP0 P51/AN1/RTP1 P60/XCIN P61/XCOUT P62/INT00 P63/TXOUT2 P64/INT2 P65/TXOUT1 P66/INT10/CNTR0 P67/CNTR1 Rev.2.00 Nov 23, 2005 REJ03B0098-0200 - - When selecting internal clock output, perform termination of output port. - - - When selecting internal clock output, perform termination of output port. - When selecting RTP function, perform termination of output port. - When selecting ADKEY function, pull-up this pin through a resistor. P52/AN2-P56/AN6 P57/AN7/ADKEY P73/PWM0/T3OUT P74/PWM1/T4OUT VL3 VL2 VL1 COM0-COM3 COM4/SEG35-COM7/SEG32 VREF Termination 3 - P41/TxD P70/C1/INT01 P71/C2/INT11 P72/T2OUT/CKOUT Termination 2 When selecting SEG output, open. Input port I/O port Connect to Vcc VL3 VL2 VL1 Connect to Vss Open Open Connect to Vcc page 21 of 75 Do not select XCIN-XCOUT oscillation - function by program. When selecting INT function, perform - termination of input port. When selecting TXOUT function, - perform termination of output port. When selecting INT function, perform - termination of input port. When selecting TXOUT function, - perform termination of output port. When selecting CNTR input function - or INT function, perform termination of input port. When selecting CNTR input function, - perform termination of input port. When selecting INT function, perform Do not select the C pin (voltage multiplir). termination of input port. When selecting T2OUT function or CKOUT - function, perform termination of output port. When selecting PWM, T3OUT, or T4OUT - function, perform termination of output port. - - - - - - - - - - - - 38C5 Group (One Time PROM version) INTERRUPTS Interrupts occur by seventeen sources: six external, ten internal, and one software. Interrupt Control Each interrupt except the BRK instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by program. Interrupt request bits can be cleared by program, but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupt requests occur at the same time, the interrupt with highest priority is accepted first. Interrupt Operation By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set to "1" and the corresponding interrupt request bit is set to "0". 3. The interrupt jump destination address is read from the vector table into the program counter. Table 8 Interrupt vector addresses and priority Vector Addresses (Note 1) Interrupt Source Priority High Low 1 FFFD16 Reset (Note 2) FFFC16 INT0 (INT00 or 2 FFFB16 FFFA16 INT01) (Note 3) INT1 (INT10 or 3 FFF916 FFF816 INT11) (Note 3) INT2 4 FFF716 FFF616 Key input (key-on wakeup) Timer X Timer 1 Timer 2 Timer 3 Timer 4 Serial I/O1 receive Serial I/O1 transmit 5 FFF516 FFF416 6 7 8 9 10 11 12 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 Serial I/O2 13 FFE516 FFE416 CNTR0 14 FFE316 FFE216 Timer Y CNTR1 15 FFE116 FFE016 A/D conversion BRK instruction 16 17 FFDF16 FFDD16 FFDE16 FFDC16 Notes on Interrupts When setting the followings, the interrupt request bit may be set to "1". *When switching external interrupt active edge Related register: Interrupt edge selection register (address 3A16) Timer X control register (address 2E16) Timer Y mode register (address 3816) *When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: Interrupt edge selection register (address 3A16) When not requiring the interrupt occurrence synchronous with these setting, take the following sequence. Set the corresponding interrupt enable bit to "0" (disabled). Set the interrupt edge selection bit (polarity switch bit) or the interrupt source selection bit. Set the corresponding interrupt request bit to "0" after 1 or more instructions have been executed. Set the corresponding interrupt enable bit to "1" (enabled). Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At detection of either rising or falling edge of INT2 input At falling of ports P20-P23, P44-P47 input logical level AND At timer X underflow At timer 1 underflow At timer 2 underflow At timer 3 underflow At timer 4 underflow At completion of serial I/O1 data receive At completion of serial I/O1 transmit shift or transmit buffer is empty At completion of serial I/O2 data transmit/receive At detection of either rising or falling edge of CNTR0 input At timer Y underflow At detection of either rising or falling edge of CNTR1 input At completion of A/D conversion At BRK instruction execution Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when INT 2 interrupt is selected External interrupt (active edge selectable) Valid when key input interrupt is selected External interrupt (falling valid) Valid only when serial I/O1 is selected Valid only when serial I/O1 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) Non-maskable software interrupt Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 3: INT0 (INT00 or INT01), INT1 (INT10 or INT11) input pins are selected by the interrupt edge selection register (INTEDGE). Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 22 of 75 38C5 Group (One Time PROM version) Interrupt request bit Interrupt enable bit Interrupt disable flag (I) Interrupt request BRK instruction Reset Fig. 18 Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 interrupt edge selection bit 0 : Falling edge active INT1 interrupt edge selection bit 1 : Rising edge active INT2 interrupt edge selection bit Timer Y/CNTR1 interrupt switch bit 0 : Timer Y interrupt 1 : CNTR1 interrupt INT0 input port switch bit 0 : Input from Port P62 (INT00) 1 : Input from Port P70 (INT01) INT1 input port switch bit 0 : Input from Port P66 (INT10) 1 : Input from Port P71 (INT11) Not used (return "0" when read) b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) b7 b0 INT0 interrupt request bit INT1 interrupt request bit INT2 interrupt request bit Key input interrupt request bit Timer X interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Interrupt request register 2 (IREQ2 : address 003D16) Timer 4 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Serial I/O2 receive/transmit interrupt request bit CNTR0 interrupt request bit Timer Y interrupt request bit CNTR1 interrupt request bit AD conversion interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit INT1 interrupt enable bit INT2 interrupt enable bit Key input interrupt enable bit Timer X interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit b7 b0 Interrupt control register 2 (ICON2 : address 003F16) Timer 4 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Serial I/O2 receive/transmit interrupt enable bit CNTR0 interrupt enable bit Timer Y interrupt enable bit CNTR1 interrupt enable bit AD conversion interrupt enable bit Not used (returns "0" when read) (Do not write to "1".) 0 : Interrupts disabled 1 : Interrupts enabled Fig. 19 Structure of interrupt-related registers Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 23 of 75 38C5 Group (One Time PROM version) Key Input Interrupt (Key-on Wake-Up) A key input interrupt request is generated by detecting the falling edge from any pin of ports P20-P23, P44-P47 that have been set to input mode. In other words, it is generated when AND of input level goes from "1" to "0". An example of using a key input interrupt is shown in Figure 20, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P44-P47. Port PXx "L" level output Segment output disable register 1 Bit 3 = "1" Port P2 direction register bit 3 = "1" Key input control register bit 7 = "1" Key input interrupt request Port P23 latch P23 output Segment output disable register 1 Bit 2 = "1" Port P2 direction Key input control register bit 2 = "1" register bit 6 = "1" Port P22 latch P22 output Segment output disable register 1 Bit 1 = "1" Port P2 direction Key input control register bit 1 = "1" register bit 5 = "1" Port P21 latch Port P2 Input reading circuit P21 output Segment output disable register 1 Bit 0 = "1" Port P2 direction Key input control register bit 0 = "1" register bit 4 = "1" Port P20 latch P20 output Port P4 direction Key input control register bit 7 = "0" register bit 3 = "1" Port P47 latch P47 input Port P4 direction Key input control register bit 6 = "0" register bit 2 = "1" Port P4 direction Key input control register bit 4 = "0" register bit 0 = "1" Port P44 latch P46 input Port P46 latch Port P4 direction Key input control register bit 5 = "0" register bit 1 = "1" Port P45 latch P45 input P44 input Port P4 Input reading circuit PULL register 3 Bit 1 = "1" P-channel transistor for pull-up CMOS output buffer Fig. 20 Connection example when using key input interrupt Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 24 of 75 38C5 Group (One Time PROM version) A key input interrupt is controlled by the key input control register and port direction registers. When the key input interrupt is enabled, set "1" to the key input control register. A key input of any pin of ports P20-P23, P44-P47 that have been set to input mode is accepted. b7 b0 Key input control register (KIC : address 0FF7 16) P44 key input control bit P45 key input control bit P46 key input control bit P47 key input control bit P20 key input control bit P21 key input control bit P22 key input control bit P23 key input control bit 0 : Key input interrupt disabled 1 : Key input interrupt enabled Fig. 21 Structure of key input control register Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 25 of 75 38C5 Group (One Time PROM version) TIMERS 8-Bit Timer Each timer has the 8-bit timer latch. All timers are down-counters. When the timer reaches "0016", the contents of the timer latch is reloaded into the timer with the next count pulse. In this mode, the interrupt request bit corresponding to that timer is set to "1". The count can be stopped by setting the stop bit of each timer to "1". The 38C5 group has four built-in 8-bit timers : Timer 1, Timer 2, Timer 3, and Timer 4. SOURCE (Note) Timer 1 Timer 2 Timer 3 Timer 4 Frequency divider 8 Frequency division selection bits (2 bits for each Timer) Data bus Clock for Timer 4 Clock for Timer 3 Clock for Timer 2 Clock for Timer 1 XCIN Clock for Timer 1 Timer Y output "00" "01" Timer 1 count source selection bits Timer 1 latch (8) Timer 1 (8) "10" Timer 1 interrupt request Timer 1 count stop bit The following values can be selected the clock for Timer; 1/1,1/2,1/16,1/256 "00" "01" Clock for P72/T2OUT/CKOUT P72 direction register Timer 2 count source selection bits "10" Timer 2 P72 clock output control bit System clock Timer 2 output selection bit "1" "0" Q S 1/2 T "1" "0" Q T2OUT output P72 edge switch bit latch Timer 2 latch (8) Timer 2 (8) Timer 2 write control bit Timer 2 interrupt request Timer 2 count stop bit Timer 2 output selection bit "1" Timer 3 operating mode selection bit "1" Timer 3 latch (8) Timer 3 (8) Clock for Timer 3 P73/PWM0/ T3OUT Timer 3 count source selection bit "0" Timer 3 write control bit Timer 3 interrupt request Timer 3 count stop bit 10 bit PWM0 circuit Timer 3 output selection bit PWM01 register (2) "0" "0" S Q P 73 T "1" latch Q 1/2 T3OUT output Timer 3 output selection bit edge switch bit P73 direction register "01" "10" Clock for Timer 4 P74/PWM1/ T4OUT Timer 4 operating mode selection bit "1" 10 bit PWM1 circuit Timer 4 count source selection bits "11" "00" Timer 4 latch (8) Timer 4 (8) Timer 4 write control bit Timer 4 interrupt request Timer 4 count stop bit f(XIN) Timer 4 output selection bit PWM01 register (2) "0" "0" S P 74 Q T "1" latch 1/2 Q T4OUT output edge switch bit Timer 4 output selection bit P74 direction register Fig. 22 Structure of timer related register Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 26 of 75 SOURCE: represents the oscillation frequency of XIN input in the middle- and high-speed mode, on-chip oscillator divided by 4 in the on-chip oscillator mode, and sub-clock in the low-speed mode. 38C5 Group (One Time PROM version) Frequency Divider For Timer Timer 3 PWM0 Mode, Timer 4 PWM1 Mode Timer 1, timer 2, timer 3 and timer 4 have the frequency divider for the count source. The count source of the frequency divider is switched to XIN, XCIN, or the on-chip oscillator (ROSC) divided by 4 in the onchip oscillator mode by the CPU mode register. The frequency divider is controlled by each timer division ratio selection bit. The division ratio can be selected from as follows; 1/1, 1/2, 1/16, 1/256 of f(XIN), f(XCIN) or f(ROSC)/4. Stop a timer to switch the division of frequency. A PWM rectangular waveform corresponding to the 10-bit accuracy can be output from the P73/PWM0 pin and P74/PWM1 pin by setting the timer 34 mode register and PWM01 register (refer to Figure 23). One output pulse is the short interval. Four output pulses are the long interval. The "n" is the value set in the timer 3 (address 002216) or the timer 4 (address 002316). The "ts" is one period of timer 3 or timer 4 count source. "H" width of the short interval is obtained by n ts. However, in the long interval, "H" width of output pulse is extended for ts which is set by the PWM01 register (address 002416). Timer 1, Timer 2 The count sources of timer 1 and timer 2 can be selected by setting the timer 12 mode register. When XCIN is selected as the count source, a pulse input from XCIN can be counted. Also, by the timer 12 mode register, each time timer 2 underflows, the signal of which polarity is inverted can be output from P72/T2OUT pin. At reset, all bits of the timer 12 mode register are set to "0," timer 1 is set to "FF16", and timer 2 is set to "0116". When executing the STP instruction, previously set the wait time at return. Timer 3, Timer 4 The count sources of timer 3 and timer 4 can be selected by setting the timer 34 mode register. Also, by the timer 34 mode register, each time timer 3 or timer 4 underflows, the signal of which polarity is inverted can be output from P73/T3OUT pin or P74/T4OUT pin. Notes on Timer 3 PWM0 Mode, Timer 4 PWM1 Mode When PWM output is suspended after starting PWM output, depending on the level of the output pulse at that time to resume an output, the delay of the one section of the short interval may be needed. Stop at "H": No output delay Stop at "L": Output is delayed time of 256 ts In the PWM mode, the follows are performed every cycle of the long interval (4 256 ts). *Generation of timer 3, timer 4 interrupt requests *Update of timer 3, timer 4 Writing to Timer 2, Timer 3, Timer 4 When writing to the latch only, if the write timing to the reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. In this time, counting is stopped during writing to the reload latch. Output waveform of Timer 3 PWM0 or Timer 4 PWM1 Long interval 4 256 ts PWM01 register = "002" Short interval 256 ts Short interval 256 ts Short interval 256 ts n ts n ts n ts n ts n ts n ts PWM01 register = "012" (n+1) ts n ts PWM01 register = "102" (n+1) ts n ts PWM01 register = "112" (n+1) ts Interrupt request (n+1) ts Short interval 256 ts (n+1) ts n ts (n+1) ts n ts Interrupt request n: Setting value of Timer 3 or Timer 4 ts: One period of Timer 3 count source or Timer 4 count source PWM01 register (address 002416) : 2-bit value corresponding to PWM0 (bits 0, 1) or PWM1 (bits 2, 3) Fig. 23 Waveform of PWM0 and PWM1 Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 27 of 75 38C5 Group (One Time PROM version) b7 b7 b0 b0 Timer 12 mode register (T12M: address 002516) PWM01 register (PWM01: address 002416) Timer 1 count stop bit 0 : Count operation 1 : Count stop Timer 2 count stop bit 0 : Count operation 1 : Count stop Timer 1 count source selection bits b3 b2 0 0 : Frequency divider for Timer 1 0 1 : f(XCIN) 1 0 : Underflow of Timer Y 1 1 : Not available Timer 2 count source selection bits b5 b4 0 0 : Underflow of Timer 1 0 1 : f(XCIN) 1 0 : Frequency divider for Timer 2 1 1 : Not available Timer 2 output selection bit (P72) 0 : I/O port 1 : Timer 2 output T2OUT output edge switch bit 0 : Start at "L" output 1 : Start at "H" output b7 b7 b0 Timer 34 mode register (T34M: address 002616) Timer 3 count stop bit 0 : Count operation 1 : Count stop Timer 4 count stop bit 0 : Count operation 1 : Count stop Timer 3 count source selection bit 0 : Frequency divider for Timer 3 1 : Underflow of Timer 2 Timer 4 count source selection bits b4 b3 0 0 : Frequency divider for Timer 4 0 1 : Underflow of Timer 3 1 0 : Underflow of Timer 2 1 1 : f(XIN) Timer 3 operating mode selection bit 0 : Timer mode 1 : PWM mode Timer 4 operating mode selection bit 0 : Timer mode 1 : PWM mode Not used (returns "0" when read) b7 PWM0 set bits b1 b0 0 0 : No extended 0 1 : Extended once in four periods 1 0 : Extended twice in four periods 1 1 : Extended three times in four periods PWM1 set bits b3 b2 0 0 : No extended 0 1 : Extended once in four periods 1 0 : Extended twice in four periods 1 1 : Extended three times in four periods Not used (returns "0" when read) b0 Timer 1234 mode register (T1234M: address 002716) T3OUT output edge switch bit 0 : Start at "L" output 1 : Start at "H" output T4OUT output edge switch bit 0 : Start at "L" output 1 : Start at "H" output Timer 3 output selection bit (P73) 0 : I/O port 1 : Timer 3 output Timer 4 output selection bit (P74) 0 : I/O port 1 : Timer 4 output Timer 2 write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Timer 3 write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Timer 4 write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Not used (returns "0" when read) Fig. 24 Structure of Timer 1 to timer 4 related registers Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 28 of 75 b0 Timer 1234 frequency division selection register (PRE1234: address 002816) Timer 1 frequency division selection bits b1 b0 0 0 : 1/16 SOURCE 0 1 : 1/1 SOURCE 1 0 : 1/2 SOURCE 1 1 : 1/256 SOURCE Timer 2 frequency division selection bits b3 b2 0 0 : 1/16 SOURCE 0 1 : 1/1 SOURCE 1 0 : 1/2 SOURCE 1 1 : 1/256 SOURCE Timer 3 frequency division selection bits b5 b4 0 0 : 1/16 SOURCE 0 1 : 1/1 SOURCE 1 0 : 1/2 SOURCE 1 1 : 1/256 SOURCE Timer 4 frequency division selection bits b7 b6 0 0 : 1/16 SOURCE 0 1 : 1/1 SOURCE 1 0 : 1/2 SOURCE 1 1 : 1/256 SOURCE Note: SOURCE: represents the oscillation frequency of XIN input in the middle- and high-speed mode, on-chip oscillator divided by 4 in the on-chip oscillator mode, and sub-clock in the low-speed mode. 38C5 Group (One Time PROM version) 16-bit Timer Read and write operation on 16-bit timer must be performed for both high and low-order bytes. When reading a 16-bit timer, read the highorder byte first. When writing to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing during the read operation. XIN Noise filter sampling clock selection bit "1" Trigger for IGBT control bit 1/4 Frequency divider SOURCE 2 Frequency divider 1/2 Timer X frequency division selection bits Data bus "1" X2 "0" "0" INT0 interrupt request Delay time selection bits 0 s Noise filter (4 times same levels judgment) Edge selection * INT00/INT01 "00" Delay 4/f(XIN) circuit 8/f(XIN) Trigger for IGBT control bit "01" "10" Delay circuit 1/2 "1" 16/f(XIN) "11" "0" Clock for Timer X "0" Count source selection bit XcIN "000" "001" "011" "100" "101" "1" Timer X operating mode bits D Q Data for control of event counter window "000" "001" "010" "011" "101" Timer 1 interrupt Latch "00" CNTR0 "01" Both edges detection "10" "11" Timer X count stop bit Timer X (low-order) latch (8) Timer X (high-order) latch (8) Extend latch (2) Timer X (low-order)(8) Extend counter (2) Timer X interrupt request CNTR0 interrupt request Timer X operating "010" mode bits Edge detection Edge selection * Timer X output control bit 2 Edge selection * INT2 Timer X (high-order)(8) Pulse width measurement mode Timer X output control bit 1 INT10/INT11 Timer X write control bit "100" CNTR0 active edge switch bits Compare register 1 (low-order)(8) Compare register 1 (high-order)(8) Compare register 2 (low-order)(8) Compare register 2 (high-order)(8) Compare register 3 (low-order)(8) Compare register 3 (high-order)(8) Q R S T Q "0" Pulse output mode P65/TXOUT1/(LED3) Q "1" P 65 direction register P65 latch Timer X output 1 edge switch bit Timer X output 1 selection bit S S T Q IGBT output mode PWM mode "0" Q R S T P63/TXOUT2/(LED1) "1" P 63 direction register P63 latch Timer X output 2 edge switch bit Timer X output 2 selection bit SOURCE: represents the supply source of internal clock . XIN input: in the middle- or high-speed mode, Internal on-chip oscillator divided by 4 in the on-chip oscillator mode, and Sub clock in the low-speed mode. Fig. 25 Structure of timer related register Rev.2.00 Nov 23, 2005 REJ03B0098-0200 Timer X operating "010" mode bits page 29 of 75 Q Equal 38C5 Group (One Time PROM version) Frequency Divider For Timer Each timer X and timer Y have the frequency dividers for the count source. The count source of the frequency divider is switched to XIN, XCIN, or the on-chip oscillator in the on-chip oscillator mode by the CPU mode register. The division ratio of each timer can be controlled by each timer division ratio selection bit. The division ratio can be selected from as follows; 1/1, 1/2, 1/16, 1/256 of f(XIN), f(XCIN) or f(ROSC)/4. Timer X The timer X count source can be selected by setting the timer X mode register. When XCIN is selected as the count source, a pulse input from XCIN can be counted. The timer X operates as down-count. When the timer contents reach "000016", an underflow occurs at the next count pulse and the timer latch contents are reloaded. After that, the timer continues countdown. When the timer underflows, the interrupt request bit corresponding to the timer X is set to "1". Six operating modes can be selected for timer X by the timer X mode register and timer X control register. (4) PWM Mode IGBT dummy output, an external trigger with the INT0 pin and output control with pins INT1 and INT2 are not used. Except for those, this mode operates just as in the IGBT output mode. The period of PWM waveform is specified by the timer X set value. In the case that the timer X1 output edge switch bit is "0", the "H" interval is specified by the compare register 1 set value. In the case that the timer X2 output edge switch bit is "0", the "H" interval is specified by the compare registers 2 and 3 set values. When using this mode, set the port sharing the pin used as TXOUT1 or TXOUT2 function to output mode. Do not write "1" to the timer X register (extension) when using the PWM mode. (5) Event Counter Mode The count source can be selected by setting the timer X mode register. In this mode, timer X operates as the 18-bit counter by setting the timer X register (extension). The timer counts signals input through the CNTR0 pin. In this mode, timer X operates as the 18-bit counter by setting the timer X register (extension). When using this mode, set the port sharing the CNTR0 pin to input mode. In this mode, the window control can be performed by the timer 1 underflow. When the bit 5 (data for control of event counter window) of the timer X mode register is set to "1", counting is stopped at the next timer 1 underflow. When the bit is set to "0", counting is restarted at the next timer 1 underflow. (2) Pulse Output Mode (6) Pulse Width Measurement Mode Pulses of which polarity is inverted each time the timer underflows are output from the TXOUT1 pin. Except for that, this mode operates just as in the timer mode. When using this mode, set the port sharing the TXOUT1 pin to output mode. In this mode, the count source is the output of frequency divider for timer. In this mode, timer X operates as the 18-bit counter by setting the timer X register (extension). When the bit 6 of the CNTR0 active edge switch bits is "0", counting is executed during the "H" interval of CNTR0 pin input. When the bit is "1", counting is executed during the "L" interval of CNTR0 pin input. When using this mode, set the port sharing the CNTR0 pin to input mode. (1) Timer Mode (3) IGBT Output Mode After dummy output from the TXOUT1 pin, count starts with the INT0 pin input as a trigger. In the case that the timer X1 output edge switch bit is "0", when the trigger is detected or the timer X underflows, "H" is output from the TXOUT1 pin. And then, when the count value corresponds with the compare register 1 value, the TXOUT1 output becomes "L". After noise is cleared by noise filters, judging continuous 4-time same levels with sampling clocks to be signals, the INT0 signal can use 4 types of delay time by a delay circuit. When using this mode, set the port sharing the INT0 pin to input mode and set the port sharing the pin used as TXOUT1 or TXOUT2 function to output mode. When the timer X output control bit 1 or 2 of the timer X control register is set to "1", the timer X count stop bit is fixed to "1" forcibly by the interrupt signal of INT1 or INT2. And then, the TXOUT1 output and TXOUT2 output can be set to "L" forcibly at the same time that the timer X stops counting. Do not write "1" to the timer X register (extension) when using the IGBT output mode. Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 30 of 75 38C5 Group (One Time PROM version) ts Timer X count source Timer X PWM mode IGBT output mode External trigger (INT0 source) is generated. TXOUT1 output (TXCON1 bit 5 = "1") INT1 or INT2 source is generated. Level is "H" only IGBT output mode. m ts Level is forcibly "L" only IGBT output mode. TXOUT2 output (TXCON2 bit 1 = "0") q ts p ts (n+1) ts n : Timer X setting value m: Compare register 1 setting value p : Compare register 2 setting value q : Compare register 3 setting value ts: One period of timer X count source The following PWM waveform is output; Duty of TXOUT1 output :{(n+1)-m}/(n+1), Duty of TXOUT2 output :(p-q)/(n+1), Period :(n+1) ts Fig. 26 Waveform of PWM/IGBT Notes on Timer X (1) Write Order to Timer X * In the timer mode, pulse output mode, event counter mode and pulse width measurement mode, write to the following registers in the order as shown below; the timer X register (extension), the timer X register (low-order), the timer X register (high-order). Do not write to only one of them. When the above mode is set and timer X operates as the 16-bit counter, if the timer X register (extension) is never set after reset is released, setting the timer X register (extension) is not required. In this case, write the timer X register (low-order) first and the timer X register (high-order). However, once writing to the timer X register (extension) is executed, note that the value is retained to the reload latch. * In the IGBT output and PWM modes, do not write "1" to the timer X register (extension). Also, when "1" is already written to the timer X register, be sure to write "0" to the register before using. Write to the following registers in the order as shown below; the compare registers 1, 2, 3 (high- and low-order), the timer X register (extension), the timer X register (low-order), the timer X register (high-order). It is possible to use whichever order to write to the compare registers 1, 2, 3 (high- and low-order). However, write both the compare registers 1, 2, 3 and the timer X register at the same time. Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 31 of 75 (2) Read Order to Timer X * In all modes, read the following registers in the order as shown below; the timer X register (extension), the timer X register (high-order), the timer X register (low-order). When reading the timer X register (extension) is not required, read the timer X register (high-order) first and the timer X register (loworder). Read order to the compare registers 1, 2, 3 is not specified. * Write to or read from the timer X register by the 16-bit unit. If reading to the timer X register during write operation or writing to it during read operation is performed, normal operation will not be performed. (3) Write to Timer X * Which write control can be selected by the timer X write control bit (b3) of the timer X mode register (address 2D16), writing data to both the latch and the timer at the same time or writing data only to the latch. When writing a value to the timer X address to write to the latch only, the value is set into the reload latch and the timer is updated at the next underflow. After reset release, when writing a value to the timer X address, the value is set into the timer and the timer latch at the same time, because they are written at the same time. When writing to the latch only, if the write timing to the high-order reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. In this time, counting is stopped during writing to the high-order reload latch. * Do not switch the timer count source during timer count operation. Stop the timer count before switching it. 38C5 Group (One Time PROM version) (4) Set of Timer X Mode Register Set the write control bit of the timer X mode register to "1" (write to the latch only) when setting the IGBT output and PWM modes. Output waveform simultaneously reflects the contents of both registers at the next underflow after writing to the timer X register (highorder). (5) Output Control Function of Timer X * When using the output control function (INT1 and INT2) in the IGBT output mode, set the levels of INT1 and INT2 to "H" in the falling edge active or to "L" in the rising edge active before switching to the IGBT output mode. (6) Switch of CNTR0 Active Edge * When the CNTR0 active edge switch bits are set, at the same time, the interrupt active edge is also affected. * When the pulse width is measured, set the bit 7 of the CNTR0 active edge switch bits to "0". b7 b0 b7 Timer X mode register (TXM: address 002D16) Timer X operating mode bits b2 b1 b0 0 0 0 : Timer mode 0 0 1 : Pulse output mode 0 1 0 : IGBT output mode 0 1 1 : PWM mode 1 0 0 : Event counter mode 1 0 1 : Pulse width measurement mode 1 1 0 : Not available 1 1 1 : Not available Timer X write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Timer X count source selection bit 0 : Frequency divider output 1 : f(XCIN) Data for control of event counter window 0 : Event count enabled 1 : Event count disabled Timer X count stop bit 0 : Count operation 1 : Count stop Timer X output 1 selection bit (P65) 0 : I/O port 1 : Timer X output 1 b7 b0 Timer X control register 2 (TXCON2: address 002F16) Timer X output 2 selection bit (P63) 0 : I/O port 1 : Timer X output 2 Timer X output 2 active edge switch bit 0 : Start at "L" output 1 : Start at "H" output Timer X diving frequency selection bits b3 b2 0 0 : 1/16 SOURCE 0 1 : 1/1 SOURCE (Note) 1 0 : 1/2 SOURCE 1 1 : 1/256 SOURCE Trigger for IGBT input control bit 0 : Noise filter sampling clock 1 External trigger delay time 1 1 : Noise filter sampling clock 2 External trigger delay time 1/2 Not used (returns "0" when read) Fig. 27 Structure of Timer X related registers Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 32 of 75 b0 Timer X control register 1 (TXCON1: address 002E16) Noise filter sampling clock selection bit 0 : f(XIN)/2 1 : f(XIN)/4 External trigger delay time selection bits b2 b1 0 0 : Not delayed 0 1 : (4/f(XIN)) s 1 0 : (8/f(XIN)) s 1 1 : (16/f(XIN)) s Timer X output 1 control bit (P66 or P71) 0 : Not used 1 : INT1 interrupt used Timer X output 2 control bit (P64) 0 : Not used 1 : INT2 interrupt used Timer X output 1 edge switch bit 0 : Start at "L" output 1 : Start at "H" output CNTR0 active edge switch bits b7 b6 0 0 : Count at rising edge in event counter mode Falling edge active for CNTR0 interrupt Measure "H" pulse width in pulse width measurement mode 0 1 : Count at falling edge in event counter mode Rising edge active for CNTR0 interrupt Measure "L" pulse width in pulse width measurement mode 1 0: Count at both edges in event counter mode 1 1: Both edges active for CNTR0 interrupt SOURCE: represents the supply source of internal clock . XIN input: in the middle- or high-speed mode, Internal on-chip oscillator divided by 4 in the on-chip oscillator mode, and Sub clock in the low-speed mode. 38C5 Group (One Time PROM version) Data bus 2 SOURCE Frequency divider Timer Y operating mode bits Timer Y dividing frequency selection bit "00", "01", "10" "0" Rising edge detection "1" XcIN Count source selection bit Falling edge detection Pulse width HL continuous measurement mode CNTR1 interrupt request "11" Period measurement mode Timer Y write control bit Timer Y count stop bit CNTR1 active edge switch bit AA AA "00", "01", "11" "0" CNTR1 "10" "1" Timer Y (low-order) latch (8) Timer Y (high-order) latch (8) Timer Y (low-order)(8) Real time port 2 control bit "1" "0" "0" "0" Timer Y mode register write signal Latch "1" Real time port 1 control bit Q D P50/RTP0/AN0 P50 direction register P51 data for real time port P51 latch Real time port 1 control bit "1" Timer Y interrupt request Real time port 2 control bit Q D P51/RTP1/AN1 P51 direction register Timer Y (high-order)(8) Timer Y operating mode bits P50 data for real time port "0" Timer Y mode register write signal Latch "1" P50 latch Fig. 28 Block diagram of Timer Y Timer Y (3) Event Counter Mode Timer Y is a 16-bit timer. The timer Y count source can be selected by setting the timer Y mode register. When f(XCIN) is selected as the count source, counting can be performed regardless of XCIN oscillation. However, when XCIN is stopped, the external pulse input from XCIN pin is counted. Four operating modes can be selected for timer Y by the timer Y mode register. Also, the real time port can be controlled. The timer counts signals input through the CNTR1 pin. Except for that, this mode operates just as in the timer mode. When using this mode, set the port sharing the CNTR1 pin to input mode. (1) Timer Mode The timer Y count source can be selected by setting the timer Y mode register. (2) Period Measurement Mode The interrupt request is generated at rising or falling edge of CNTR1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting. Except for that, this mode operates just as in the timer mode. The timer value just before the reloading at rising or falling of CNTR1 pin input is retained until the timer Y is read once after the reload. The rising or falling timing of CNTR1 pin input is found by CNTR1 interrupt. When using this mode, set the port sharing the CNTR1 pin to input mode. Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 33 of 75 (4) Pulse Width HL Continuously Measurement Mode The interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for that, this mode operates just as in the period measurement mode. When using this mode, set the port sharing the CNTR1 pin to input mode. 38C5 Group (One Time PROM version) Notes on Timer Y CNTR1 Interrupt Active Edge Selection CNTR1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit. Timer Y Read/Write Control Real Time Port Control When the real time port function is valid, data for the real time port is output from ports P50 and P51 each time the timer Y underflows. (However, if the real time port control bit is changed from "0" to "1" after the data for real time port is set, data is output independent of the timer Y operation.) When the data for the real time port is changed while the real time port function is valid, the changed data is output at the next underflow of timer Y. Before using this function, set the corresponding port direction registers to output mode. * When reading from/writing to timer Y, read from/write to both the high-order and low-order bytes of timer Y. When the value is read, read the high-order bytes first and the low-order bytes next. When the value is written, write the low-order bytes first and the highorder bytes next. Write to or read from the timer X register by the 16-bit unit. If reading from the timer Y register during write operation or writing to it during read operation is performed, normal operation will not be performed. * Which write control can be selected by the timer Y write control bit (b0) of the timer Y control register (address 003916), writing data to both the latch and the timer at the same time or writing data only to the latch. When writing a value to the timer Y address to write to the latch only, the value is set into the reload latch and the timer is updated at the next underflow. After reset release, when writing a value to the timer Y address, the value is set into the timer and the timer latch at the same time, because they are set to write at the same time. When writing to the latch only, if the write timing to the high-order reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. In this time, counting is stopped during writing to the high-order reload latch. * Do not switch the timer count source during timer count operation. Stop the timer count before switching it. b7 b7 b0 Timer Y mode register (TYM: address 003816) Real time port 1 control bit (P50) 0 : Real time port function invalid 1 : Real time port functin valid Real time port 2 control bit (P51) 0 : Real time port function invalid 1 : Real time port functin valid P50 data for real time port P51 data for real time port Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuous measurement mode CNTR1 active edge switch bit 0 : Count at rising edge in event counter mode Measure falling period in period measurement mode Falling edge active for CNTR1 interrupt 1 : Count at falling edge in event counter mode Measure rising period in period measurement mode Rising edge active for CNTR1 interrupt Timer Y count stop bit 0 : Count operation 1 : Count stop Fig. 29 Structure of Timer X related registers Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 34 of 75 b0 Timer Y control register (TYCON: address 003916) Timer Y write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Timer Y count source selection bit 0 : Frequency divider output 1 : f(XCIN) Timer Y frequency division selection bits b3 b2 0 0 : 1/16 SOURCE 0 1 : 1/1 SOURCE 1 0 : 1/2 SOURCE 1 1 : 1/256 SOURCE Not used (returns "0" when read) SOURCE:represents the supply source of internal clock . XIN input: in the middle- or high-speed mode, Internal on-chip oscillator divided by 4 in the on-chip oscillator mode, and Sub clock in the low-speed mode. 38C5 Group (One Time PROM version) (1) Clock Synchronous Serial I/O Mode SERIAL INTERFACE Serial I/O1 Clock synchronous serial I/O1 mode can be selected by setting the serial I/O mode selection bit of the serial I/O1 control register to "1". For clock synchronous serial I/O1, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. Data bus Address 001816 Serial I/O1 control register Receive buffer register Receive buffer full flag (RBF) Receive interrupt request (RI) Receive shift register P40/RXD Shift clock Address 001A16 Clock control circuit P42/SCLK1 SOURCE Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) BRG count source selection bit Baud rate generator Address 001C16 1/4 P43/SRDY1 F/F 1/4 Clock control circuit Falling-edge detector Shift clock Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register P41/TXD Transmit buffer register Address 001816 Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Data bus SOURCE:represents the supply source of internal clock . XIN input: in the middle- or high-speed mode, Internal on-chip oscillator divided by 4 in the on-chip oscillator mode, and Sub clock in the low-speed mode. Fig. 30 Block diagram of clock synchronous serial I/O1 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD D0 D1 D2 D3 D4 D5 D6 D7 Serial input RxD D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY Write pulse to receive/transmit buffer register TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1: As the transmit interrupt (TI) source, which can be selected, either when the transmit buffer has emptied (TBE = 1) or after the transmit shift operation has ended (TSC = 1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" . Fig. 31 Operation of clock synchronous serial I/O1 function Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 35 of 75 38C5 Group (One Time PROM version) (2) Asynchronous Serial I/O (UART) Mode two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Clock asynchronous serial I/O mode (UART) can be selected by setting the serial I/O mode selection bit of the serial I/O1 control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the Data bus Address 001816 P40/RXD Serial I/O1 control register Receive buffer register OE Character length selection bit ST detector 7 bits Receive shift register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 8 bits PE FE UART control register Address 001B16 SP detector Clock control circuit Serial I/O1 synchronous clock selection bit P42/SCLK1 SOURCE BRG count source selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 1/4 ST/SP/PA generator Transmit shift completion flag (TSC) 1/16 P41/TXD Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register Character length selection bit Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Transmit buffer register Address 001816 Data bus SOURCE:represents the supply source of internal clock . XIN input: in the middle- or high-speed mode, Internal on-chip oscillator divided by 4 in the on-chip oscillator mode, and Sub clock in the low-speed mode. Fig. 32 Block diagram of UART serial I/O1 Transmit or receive clock Transmit buffer register write signal TBE=0 TSC=0 TBE=1 Serial output TXD TBE=0 TSC=1 TBE=1 ST D0 D1 SP ST D0 SP D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) Generated at 2nd bit in 2-stop-bit mode Receive buffer register read signal RBF=0 RBF=1 Serial input RXD ST D0 D1 SP RBF=1 ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1," can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1". 4: After data is written to the transmit buffer when TSC flag ="1", 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC flag = "0". Fig. 33 Operation of UART serial I/O1 function Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 36 of 75 38C5 Group (One Time PROM version) [Transmit Buffer Register/Receive Buffer Register (TB/RB)] The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0". [Serial I/O1 Status Register (SIO1STS)] The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is set to "0" when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register sets all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively) to "0". Writing "0" to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also sets all the status flags to "0", including the error flags. All bits of the serial I/O1 status register are set to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1". [Serial I/O1 Control Register (SIO1CON)] The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART Control Register (UARTCON)] The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P41/TXD pin. [Baud Rate Generator (BRG)] The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 37 of 75 Notes on serial I/O1 When setting transmit enable bit of serial I/O1 to "1", the serial I/O1 transmit interrupt request bit is automatically set to "1". When not requiring the interrupt occurrence synchronous with the transmision enabled, take the following sequence. Set the serial I/O1 transmit interrupt enable bit to "0" (disabled). Set the transmit enable bit to "1". Set the serial I/O1 transmit interrupt request bit to "0" after 1 or more instructions have been executed. Set the serial I/O1 transmit interrupt enable bit to "1" (enabled). 38C5 Group (One Time PROM version) b7 b0 Serial I/O1 status register (SIO1STS : address 001916) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Serial I/O1 control register (SIO1CON : address 001A16) BRG count source selection bit (CSS) 0: SOURCE (Note) 1: SOURCE/4 Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error SRDY1 output enable bit (SRDY) 0: P43 pin operates as ordinary I/O pin 1: P43 pin operates as SRDY1 output pin Parity error flag (PE) 0: No error 1: Parity error Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read) b0 b0 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected. BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected. External clock input divided by 16 when UART is selected. Framing error flag (FE) 0: No error 1: Framing error b7 b7 UART control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit ( PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P41/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read) Fig. 34 Structure of serial I/O1 related registers Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 38 of 75 Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P40 to P43 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P40 to P43 operate as serial I/O pins) SOURCE: represents the supply source of internal clock . XIN input: in the middle- or high-speed mode, Internal on-chip oscillator divided by 4 in the on-chip oscillator mode, and Sub clock in the low-speed mode. 38C5 Group (One Time PROM version) Serial I/O2 b7 b0 The serial I/O2 function can be used only for clock synchronous serial I/O. For serial I/O2, the transmitter and the receiver must use the same clock. When the internal clock is used, transfer is started by a write signal to the serial I/O2 register. Serial I/O2 control register (SIO2CON: address 001D16) Internal synchronous clock selection bits b2b1b0 0 0 0 : SOURCE/8 0 0 1 : SOURCE/16 0 1 0 : SOURCE/32 0 1 1 : SOURCE/64 1 0 0 : Not available 1 0 1 : Not available 1 1 0 : SOURCE/128 1 1 1 : SOURCE/256 Serial I/O2 port selection bit 0 : I/O port 1 : SOUT2, SCLK2 signal pin P45/SOUT2 P-channel output disable bit 0 : CMOS output (at output mode) 1 : N-channel open-drain output (at output mode) [Serial I/O2 control register] SIO2CON The serial I/O2 control register contains 8 bits which control various serial I/O functions. Transfer direction selection bit 0 : LSB first 1 : MSB first Serial I/O2 synchronous clock selection bit 0 : External clock 1 : Internal clock SRDY2 output selection bit 0 : I/O port P47 1 : SRDY2 signal output SOURCE: represents the supply source of internal clock . XIN input: in the middle- or high-speed mode, Internal on-chip oscillator divided by 4 in the on-chip oscillator mode, and Sub clock in the low-speed mode. Fig. 35 Structure of serial I/O2 control registers 1/8 Internal synchronous clock selection bits Data bus 1/16 Frequency 1/32 1/64 divider 1/128 1/256 SOURCE P47 latch Serial I/O2 synchronous clock selection bit "1" (Note) P47/SRDY2 SCLK2 Synchronous circuit "0" External clock P46 latch "0 " P46/SCLK2 (Note) "1 " Serial I/O counter 2 (3) P45 latch "0 " P45/SOUT2 "1 " Serial I/O2 port selection bit Serial I/O shift register 2 (8) P44/SIN2 Note: It is selected by the serial I/O2 synchronous clock selection bit, SRDY2 output selection bit and serial I/O2 port selection bit. Fig. 36 Block diagram of serial I/O2 Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 39 of 75 Serial I/O2 interrupt request 38C5 Group (One Time PROM version) Transfer clock (Note 1) Serial I/O2 register write signal (Note 2) Serial I/O2 output SOUT2 D0 D1 D2 D3 D4 D5 D6 D7 Serial I/O2 input SIN2 Serial I/O2 interrupt request bit set 1: When the internal clock is selected as the transfer, the dividing frequency of internal clock for transfer clock can be selected by bits 0 to 2 of serial I/O2 control register. 2: When the internal clock is selected as the transfer, the SOUT2 pin is in a high impedance state after the data transfer is completed. When the external clock is selected as the transfer, the contents of serial I/O shift register keeps shifting during the transmit/receive clock is input. Also, the SOUT2 pin is not in a high impedance state after the data transfer is completed. Fig. 37 Serial I/O2 timing Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 40 of 75 38C5 Group (One Time PROM version) A/D CONVERTER [Channel Selector] The 38C5 group has a 10-bit A/D converter. The A/D converter performs successive approximation conversion.The 38C5 group has the ADKEY function which perform A/D conversion of the "L" level analog input from the ADKEY pin automatically. The channel selector selects one of the input ports P57/AN7-P50/ AN0 and inputs it to the comparator. [AD Conversion Register (ADL, ADH)] One of these registers is a high-order register, and the other is a loworder register. The high-order 8 bits of a conversion result is stored in the AD conversion register (high-order) (address 001716), and the low-order 2 bits of the same result are stored in bit 7 and bit 6 of the AD conversion register (low-order) (address 001616). During A/D conversion, do not read these registers. Also, the connection between the resistor ladder and reference voltage input pin (VREF) can be controlled by the VREF input switch bit (bit 0 of address 001616). When "1" is written to this bit, the resistor ladder is always connected to VREF. When "0" is written to this bit, the resistor ladder is disconnected from VREF except during the A/D conversion. [Comparator and Control Circuit] The comparator and control circuit compare an analog input voltage with the comparison voltage and store the result in the AD conversion register. When an A/D conversion is completed, the control circuit sets the AD conversion completion bit and the AD conversion interrupt request bit to "1." The comparator is constructed linked to a capacitor. The conversion accuracy may be low because the change is lost if the conversion speed is not enough. Accordingly, set f(XIN) to at least 500 kHz during A/D conversion in the middle- or high- speed mode. Also, do not execute the STP and WIT instructions during the A/D conversion. In the low-speed mode, since the A/D conversion is executed by the built-in self-oscillation circuit, the minimum value of f(XIN) frequency. [AD Control Register (ADCON)] This register controls A/D converter. Bits 2 to 0 are analog input pin selection bits. Bit 3 is an AD conversion completion bit and "0" during A/ D conversion. This bit is set to "1" upon completion of A/D conversion. A/D conversion is started by setting "0" in this bit. Bit 5 is the ADKEY enable bit. The ADKEY function is enabled by setting "1" to this bit. When this function is valid, the analog input selection bit is ignored. Also, when bit 5 is "1", do not set "0" to bit 3 by program. [Comparison Voltage Generator] The comparison voltage generator divides the voltage between AVSS and VREF, and outputs the divided voltages. Data bus b7 b0 AD control register ADKEY control circuit Comparator AD conversion register (H) AD conversion register (L) (Address 001716) Resistor ladder AVSS Fig. 38 Block diagram of A/D converter Rev.2.00 Nov 23, 2005 REJ03B0098-0200 A/D interrupt request A/D control circuit Channel selector P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7/ADKEY0 page 41 of 75 VREF (Address 001616) 38C5 Group (One Time PROM version) b7 b0 AD control register (ADCON: address 001516) Analog input pin selection bits b2 b1 b0 0 0 0: P50/AN0 0 0 1: P51/AN1 0 1 0: P52/AN2 0 1 1: P53/AN3 1 0 0: P54/AN4 1 0 1: P55/AN5 1 1 0: P56/AN6 1 1 1: P57/AN7 AD conversion completion bit 0: Conversion in progress 1: Conversion completed AD conversion clock selection bit 0: SOURCE/2 (Note 1) 1: SOURCE/8 ADKEY enable bit (Note 2) 0: Disabled 1: Enabled 10-bit or 8-bit conversion switch bit 0: 10-bit AD 1: 8-bit AD ADKEY selection bit 0: Invalid 1: Valid 10-bit reading (Read address 001716 before 001616) AD conversion register 1 (Address 001716) AD conversion register 2 (Address 001616) b0 b7 b9 b8 b7 b6 b5 b4 b3 b2 (high-order) b7 b0 b1 b0 * (low-order) * VREF input switch bit 0: ON only during A/D conversion 1: ON Note : The bit 5 to bit 1 of address 001616 become "0" at reading. Also, bit 0 is undefined at reading. 8-bit reading (Read only address 001716) b7 (Address 001716) b0 b7 b6 b5 b4 b3 b2 b1 b0 Notes 1: SOURCE: represents the supply source of internal clock . XIN input: in the middle- or high-speed mode, Internal on-chip oscillator divided by 4 in the on-chip oscillator mode, and Sub clock in the low-speed mode. 2: When the ADKEY enable bit is "1", the analog input selection bit is invalid. Do not execute the A/D conversion by program while the ADKEY is enabled. Bit 0 to bit 2 of ADCON are not changed even when ADKEY is enabled. Fig. 39 Structure of AD control register Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 42 of 75 38C5 Group (One Time PROM version) ADKEY function The ADKEY function is used to judge the analog input voltage input from the ADKEY pin. When the A/D converter starts operating after VIL (0.7 Vcc-0.5) or less is input, the event of analog voltage input can be judged with the A/D conversion interrupt. This function can be used with the STP and WIT state. As for the ADKEY function in 38C5 group, the A/D conversion of analog input voltage immediately after starting ADKEY function is not performed. Therefore, the A/D conversion result immediately after an ADKEY function is undefined. Accordingly, when the A/D conversion result of the analog input voltage input from the ADKEY pin is required, start the A/D conversion by program after the analog input pin corresponding to ADKEY is selected. * ADKEY Selection When the ADKEY pin is used, set the ADKEY selection bit to "1". The ADKEY selection bit is "0", just after the A/D conversion is started. * ADKEY Enable The ADKEY function is enabled by writing "1" to the ADKEY enable bit. Surely, in order to enable ADKEY function, set "1" to the ADKEY enable bit, after setting the ADKEY selection bit to "1". When the ADKEY enable bit of the AD control register is "1", the analog input pin selection bits become invalid. Please do not write "0" in the AD conversion completion bit by the program during ADKEY enabled state. [ADKEY Control Circuit] In order to obtain a more exact conversion result, by the A/D conversion with ADKEY, execute the following; * set the input to the ADKEY pin into a steep falling waveform, * stabilize the input voltage within 8 clock cycles (1 s at f(XIN) = 8 MHz) after the input voltage is under VIL, and * maintain the input voltage until the completion of the A/D conversion. The threshold voltage with an actual ADKEY pin is the voltage between VIH-VIL. In order not to make ADKEY operation perform superfluously in a noise etc., in the state of the waiting for an input, set the voltage of an ADKEY pin to VIH (0.9VCC) or more. When the following operations are performed, the A/D conversion operation cannot be guaranteed. * When the CPU mode register is operated during A/D conversion operation, * When the AD conversion control register is operated during A/D conversion operation, * When the STP or WIT instruction is executed during A/D conversion operation. Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 43 of 75 38C5 Group (One Time PROM version) LCD DRIVE CONTROL CIRCUIT Table 9 Maximum number of display pixels at each duty ratio The 38C5 group has the built-in Liquid Crystal Display (LCD) drive control circuit consisting of the following. * LCD display RAM * Segment output disable register * LCD mode register * Selector * Timing controller * Common driver * Segment driver * Bias control circuit A maximum of 36 segment output pins and 8 common output pins can be used. Up to 256 pixels can be controlled for an LCD display. When the LCD enable bit is set to "1" after data is set in the LCD mode register, the segment output disable register, and the LCD display RAM, the LCD drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the data on the LCD panel. b7 b0 Duty ratio Maximum number of display pixels 36 dots or 8 segment LCD 4 digits 72 dots or 8 segment LCD 9 digits 108 dots or 8 segment LCD 12 digits 144 dots or 8 segment LCD 18 digits 256 dots or 8 segment LCD 32 digits 1 2 3 4 8 b7 b0 LCD mode register 2 (LM2 : address 001416) LCD mode register 1 (LM1 : address 001316) Duty ratio selection bits b2 b1 b0 0 0 0 : 1 (Static) 0 0 1 : 2 (use COM0,COM1) 0 1 0 : 3 (use COM0-COM2) 0 1 1 : 4 (use COM0-COM3) 1 0 0 to 1 1 0: Not available 1 1 1 : 8 (COM0-COM7) Bias control bit 0 : 1/3 bias (Note 1) 1 : 1/2 bias LCD enable bit 0 : LCD OFF 1 : LCD ON LCD circuit divider division ratio selection bits b6 b5 0 0 : Clock input 0 1 : 2 division of clock input 1 0 : 4 division of clock input 1 1 : 8 division of clock input LCDCK count source selection bit (Note 2) 0 : f(XCIN)/32 1 : SOURCE/8192 b7 b0 b7 Segment output disable register 0 (SEG0 : address 0FF416) Segment output disable bit 0 0 : Segment output SEG8 1 : Output port P00 Segment output disable bit 1 0 : Segment output SEG9 1 : Output port P01 Segment output disable bit 2 0 : Segment output SEG10 1 : Output port P02 Segment output disable bit 3 0 : Segment output SEG11 1 : Output port P03 Segment output disable bit 4 0 : Segment output SEG12 1 : Output port P04 Segment output disable bit 5 0 : Segment output SEG13 1 : Output port P05 Segment output disable bit 6 0 : Segment output SEG14 1 : Output port P06 Segment output disable bit 7 0 : Segment output SEG15 1 : Output port P07 Voltage multiplier circuit control bit 0 : Voltage multiplier circuit disabled (Input ports P70/INT01, P71/INT11) 1 : Voltage multiplier circuit enabled VL3 connection bit 0 : Connect VL3 to VCC. 1 : Leave VL3 and VCC open. Not available b0 Segment output disable register 1 (SEG1 : address 0FF516) Segment output disable bit 8 0 : Segment output SEG0 1 : Output port P20 Segment output disable bit 9 0 : Segment output SEG1 1 : Output port P21 Segment output disable bit 10 0 : Segment output SEG2 1 : Output port P22 Segment output disable bit 11 0 : Segment output SEG3 1 : Output port P23 Segment output disable bit 12 0 : Segment output SEG4 1 : Output port P24 Segment output disable bit 13 0 : Segment output SEG5 1 : Output port P25 Segment output disable bit 14 0 : Segment output SEG6 1 : Output port P26 Segment output disable bit 15 0 : Segment output SEG7 1 : Output port P27 Note : LCDCK is a clock for an LCD timing controller. b7 b0 Segment output disable register 2 (SEG2 : address 0FF616) Segment output disable bit 16 0 : Segment output SEG16-SEG19 1 : Output port P10-P13 Segment output disable bit 17 0 : Segment output SEG20-SEG23 1 : Output port P14-P17 Segment output disable bit 18 0 : Segment output SEG24-SEG27 1 : Output port P30-P33 Segment output disable bit 19 0 : Segment output SEG28-SEG31 1 : Output port P34-P37 Do not write "1" to these bits. Fig. 40 Structure of LCD related registers Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 44 of 75 Notes 1: When "1" is selected as duty ratio by the duty ratio selection bits, set "1" to the bias control bit. 2: LCDCK is the clock for the LCD timing controller. SOURCE represents the supply source of internal clock . XIN input: in the middle- or high-speed mode, Internal onchip oscillator divided by 4 in the on-chip oscillator mode, and Sub clock in the lowspeed mode. 3: Only pins set to output ports by the direction register can be controlled to switch to output ports or segment outputs by the segment output disable register. 4: When disabling the voltage multiplier circuit, the C1 and C2 pins function as input ports P70/INT01, P71/INT11. Rev.2.00 Nov 23, 2005 REJ03B0098-0200 Address 084116 Address 084216 Address 084316 Fig. 41 Block diagram of LCD controller/driver page 45 of 75 Level shift Level shift Level shift COM7/ SEG32 Address 086316 Level shift COM5/ SEG34 COM4/ SEG35 Segment Segment driver driver Level shift Selector Selector Address 086216 (Note 2) Level Level Level shift shift shift SEG35 SEG34 SEG33 SEG32 COM0 COM1 COM2 COM3 COM4/ COM5/ COM6/ COM7/ VL3 connection bit VSS VL1 VL2 VL3 C1 C2 Level Level Level Level shift shift shift shift Timing controller LCDCK (Note 1) LCDCK count source selection bit "0" f(XCIN)/32 LCD divider SOURCE/8192 "1" Common Common Common Common Common Common Common Common driver driver driver driver driver driver driver driver VCC Level shift 2 LCD circuit divider division ratio selection bits 2 Duty ratio selection bits LCD enable bit Bias control bit Voltage multiplier control bit Bias control LCD display RAM Notes 1: LCDCK is the clock for the LCD timing controller. SOURCE represents the supply source of internal clock . XIN input: in the middle- or high-speed mode, internal on-chip oscillator divided by 4 in the on-chip oscillator mode, and Sub clock in the low-speed mode. 2: When the voltage multiplier circuit is not used (bit 0 of LCD mode register 2 = "0"), the C1 and C2 pins function as input ports P70/INT01, P71/INT11. P20/SEG0 P21/SEG1 P22/SEG2 P23/SEG3 Segment Segment Segment Segment driver driver driver driver Level shift Selector Selector Selector Selector Address 084016 Data bus 38C5 Group (One Time PROM version) 38C5 Group (One Time PROM version) Voltage Multiplier The voltage multiplier performs threefold boosting. This circuit inputs a reference voltage for boosting from LCD power input pin V L1. Set each bit of the segment output disable registers and the LCD mode registers in the following order for operating the voltage multiplier. 1. Set the segment output disable bits (bits 0 to 19) of the segment output disable registers (SEG0, 1, 2) to "0" or "1". 2. Set the duty ratio selection bits (bits 0 to 2), the bias control bit (bit 3), the LCD circuit divider division ratio selection bits (bits 5 and 6), and the LCDCK count source selection bit (bit 7) of the LCD mode register 1 to "0" or "1". 3. Set the V L3 connection bit (bit 1 of the LCD mode register 2 (LM2)) to "1". Apply the limit voltage or less to the VL1 pin. 4. Set the voltage multiplier control bit (bit 0) of the LCD mode register 2 to "1". However, be sure to select 1/3 bias for bias control. Table 10 Bias control and applied voltage to VL1-VL3 Bias value Voltage value VL3=VLCD 1/3 bias VL2=2/3 VLCD VL1=1/3 VLCD VL3=VLCD 1/2 bias VL2=VL1=1/2 VLCD Note : VLCD is the maximum value of supplied voltage for the LCD panel. Common Pin and Duty Ratio Control The common pins (COM0-COM7) to be used are determined by duty ratio. Select duty ratio by the duty ratio selection bits (bits 0, 1 and 2 of the LCD mode register 1). When reset is released, VCC voltage is output from the common pin. Table 11 Duty ratio control and common pins used Duty ratio When voltage is input to the V L1 pin during operating the voltage multiplier, voltage that is twice as large as V L1 occurs at the VL2 pin, and voltage that is three times as large as V L1 occurs at the VL3 pin. The voltage multiplier is controlled by the voltage multiplier control bit (bit 0 of the LCD mode register 2). In addition, when the voltage multiplier is used, set the voltage multiplier control bit to "1" (voltage multiplier enabled) after the voltage 1.3 V or more and 2.1 V or less. When the voltage multiplier is not used, set the VL3 connection bit to "1" (open), and apply the suitable voltage for the power supply input pins for LCD (VL1-VL3). When VL3 connection bit is set to be opened, VL3 pin is in a high impedance state. 1 2 3 4 8 Duty ratio selection bits Bit 2 0 0 0 0 1 Bit 1 0 0 1 1 1 Bit 0 0 1 0 1 1 Common pins used COM0 COM0, COM1 COM0-COM2 COM0-COM3 COM0-COM7 Note: Unused common pin outputs the unselected waveform. Segment Signal Output Pin The segment signal output pins (SEG0-SEG31) are shared with ports P0-P3. When these pins are used as the segment signal output pins, set the direction registers of the corresponding pins to "1", and set the segment output disable register to "0". Also, these pins are set to the input port after reset, the VCC voltage is output by the pull-up resistor. Bias Control and Applied Voltage to LCD Power Input Pins Apply the voltage value shown in Table 9 according to the bias value to the LCD power input pins. Select a bias value by the bias control bit (bit 2 of the LCD mode register). Contrast adjust Contrast adjust VL3 VL3 VL3 VL3 R1 VL2 VL2 C2 P71/INT11 R4 VL2 P71/INT11 P70/INT01 VL2 R2 C1 P70/INT01 VL1 VL1 VL1 R3 R5 R4 = R5 1/3 bias: R1 = R2 = R3 1/3 bias Voltage multiplier is used. 1/3 bias Voltage multiplier is used. 1/2 bias : When the voltage multiplier is not used, the C1 and C2 pins function as input ports P70/INT01, P71/INT11. Fig. 42 Example of circuit at each bias Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 46 of 75 VL1 1/1 bias (static) 38C5 Group (One Time PROM version) LCD Display RAM The 36-byte area of address 084016 to 086316 is the designated RAM for the LCD display. When "1" is written to these addresses, the corresponding segments of the LCD display panel are turned on. The LCDCK timing frequency (LCD drive timing) is generated internally and the frame frequency can be determined with the following equation; f(LCDCK)= (frequency of count source for LCDCK) (divider division ratio for LCD) Frame frequency= f(LCDCK) duty ratio at 4COM 36SEG at 8COM 32SEG Bits Bits 7 6 5 4 3 2 1 6 5 4 3 2 1 0 Address 084016 084116 084216 084316 084416 084516 084616 084716 084816 084916 084A16 084B16 084C16 084D16 084E16 084F16 Not used (This area can be 085016 used as normal RAM.) 085116 085216 085316 085416 085516 085616 085716 085816 085916 085A16 085B16 085C16 085D16 085E16 085F16 086016 086116 086216 086316 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 COM3 COM2 COM1 COM0 Fig. 43 LCD display RAM map Rev.2.00 Nov 23, 2005 REJ03B0098-0200 7 0 Address page 47 of 75 084016 084116 084216 084316 084416 084516 084616 084716 084816 084916 084A16 084B16 084C16 084D16 084E16 084F16 085016 085116 085216 085316 085416 085516 085616 085716 085816 085916 085A16 085B16 085C16 085D16 085E16 085F16 086016 086116 086216 086316 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 Not used (This area can be used as normal RAM.) COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 38C5 Group (One Time PROM version) Internal signal LCDCK timing 1/8 duty Voltage level VL3 VL2=VL1 VSS COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 VL3 VSS SEG0 OFF COM7 ON COM6 COM5 OFF COM4 COM3 ON COM2 COM1 OFF COM0 1/4 duty COM7 ON COM6 COM5 OFF COM4 COM3 ON COM2 COM1 COM0 Voltage level VL3 VL2=VL1 VSS COM0 COM1 COM2 COM3 SEG0 VL3 VSS OFF COM3 ON COM2 COM1 OFF COM0 COM3 ON COM2 COM1 OFF COM0 COM3 ON COM2 COM1 OFF COM0 COM3 ON COM2 COM1 COM0 1/3 duty VL3 VL2=VL1 VSS COM0 COM1 COM2 VL3 VSS SEG0 ON COM0 OFF COM2 ON COM1 OFF COM0 COM2 ON COM1 OFF COM0 COM2 ON COM1 OFF COM0 ON COM2 OFF COM1 COM0 ON COM2 OFF COM1 COM0 1/2 duty VL3 VL2=VL1 VSS COM0 COM1 VL3 VSS SEG0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 Fig. 44 LCD drive waveform (1/2 bias) Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 48 of 75 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 38C5 Group (One Time PROM version) Internal signal LCDCK timing 1/8 duty Voltage level VL3 VL2 VL1 VSS COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 VL3 SEG0 VSS OFF COM7 ON COM6 COM5 OFF COM4 COM3 ON COM2 COM1 OFF COM0 COM7 ON COM6 COM5 OFF COM4 COM3 ON COM2 COM1 COM0 1/4 duty VL3 VL2 VL1 VSS COM0 COM1 COM2 COM3 VL3 SEG0 VSS OFF COM3 ON COM2 COM1 OFF COM0 COM3 ON COM2 COM1 OFF COM0 COM3 ON COM2 COM1 OFF COM0 COM3 ON COM2 COM1 COM0 1/3 duty VL3 VL2 VL1 VSS COM0 COM1 COM2 VL3 SEG0 VSS ON COM0 OFF COM2 ON COM1 OFF COM0 COM2 ON COM1 OFF COM0 COM2 ON COM0 OFF COM2 ON COM1 OFF COM0 COM2 ON COM1 OFF COM0 COM2 1/2 duty VL3 VL2 VL1 VSS COM0 COM1 VL3 SEG0 VSS ON COM1 OFF COM0 ON COM1 OFF COM0 Fig. 45 LCD drive waveform (1/3 bias) Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 49 of 75 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 38C5 Group (One Time PROM version) WATCHDOG TIMER Bit 6 of Watchdog Timer Control Register The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit counter. * When bit 6 of the watchdog timer control register is "0", the MCU enters the stop mode by execution of STP instruction. Just after releasing the stop mode, the watchdog timer restarts counting(Note). When executing the WIT instruction, the watchdog timer does not stop. * When bit 6 is "1", execution of STP instruction causes an internal reset. When this bit is set to "1" once, it cannot be rewritten to "0" by program. Bit 6 is "0" at reset. Initial Value of Watchdog Timer At reset or writing to the watchdog timer control register, each watchdog timer is set to "FF16." Instructions such as STA, LDM and CLB to generate the write signals can be used. The written data in bits 0 to 5 are not valid, and the above values are set. The time until the underflow of the watchdog timer register after writing to the watchdog timer control register is executed is as follows (when the bit 7 of the watchdog timer control register is "0") ; Standard Operation of Watchdog Timer The watchdog timer is in the stop state at reset and the watchdog timer starts to count down by writing an optional value in the watchdog timer control register. An internal reset occurs at an underflow of the watchdog timer. Then, reset is released after the reset release time is elapsed, the program starts from the reset vector address. Normally, writing to the watchdog timer control register before an underflow of the watchdog timer is programmed. If writing to the watchdog timer control register is not executed, the watchdog timer does not operate. When reading the watchdog timer control register is executed, the contents of the high-order 6-bit counter and the STP instruction disable bit (bit 6), and the count source selection bit (bit 7) are read out. * at high-speed and middle-speed mode (f(XIN)) = 8 MHz): 32.768 ms * at low-speed mode (f(XCIN) = 32 KHz): 8.19s Note The watchdog timer continues to count even during the wait time set by timer 1 and timer 2 to release the stop state and in the wait mode. Accordingly, do not underflow the watchdog timer in this time. Data bus Watchdog timer count source selection bit "0" 1/1024 Watchdog timer L (2) SOURCE Watchdog timer H (6) "1" 1/4 "FF16" is set when watchdog timer control register is written to. Undefined instruction Reset STP instruction disable bit Reset circuit STP instruction RESET Internal reset Wait until reset release Fig. 46 Block diagram of Watchdog timer b0 b7 Watchdog timer control register (WDTCON : address 002916) Watchdog timer H (for read-out of high-order 6 bit) "FF16" is set to watchdog timer by writing to these bits. STP instruction disable bit 0: Entering stop mode by execution of STP instruction 1: Internal reset by execution of STP instruction Watchdog timer count source selection bit 0: SOURCE/1024 1: SOURCE/4 Note: SOURCE represents the supply source of internal clock . XIN input: in the middle- or high-speed mode, Internal on-chip oscillator divided by 4 in the on-chip oscillator mode, and Sub clock in the low-speed mode. Fig. 47 Structure of Watchdog timer control register Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 50 of 75 38C5 Group (One Time PROM version) CLOCK OUTPUT FUNCTION b7 P72 clock output control bits Timer 2 latch (8) Timer 2 (8) S 1/2 T b0 Clock output control register (CKOUT : address 0FF316) A system clock can be output from I/O port P72.The triple function of I/O port, timer 2 output function and system clock output function are controlled by the clock output control register (address 0FF316) and the timer 2 output selection bit of the timer 12 mode register (address 002516). In order to output a system clock from I/O port P72, set the timer 2 output selection bit to "1" and P72 clock output control bits of the clock output control register to "01". In order to output the same signal as oscillation frequency of sub clock XCIN, set the P72 clock output control bits to "10". When the clock output function is selected, a clock is output while the direction register of port P72 is set to the output mode. P72 is switched to the port output or the output (timer 2 output or the clock output) except port at the cycle after the P72 clock output control bits are switched. P72 clock output control bits b1b0 0 0: Timer 2 output 0 1: frequency signal output 1 0: XCIN frequency signal output 1 1: Not available Not used (returns "0" when read) (Do not write "1" to these bits.) Fig. 48 Structure of clock output control register T2OUT output edge switch bit Q "0" "1" Q P72/T2OUT/CKOUT "00" P72 latch System clock Timer 2 output selection bit "01" XCIN "10" P72 clock output control bits Fig. 49 Block diagram of Clock output function Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 51 of 75 P72 direction register b7 b0 Timer 12 mode register (address 002516) T12M Timer 2 output selection bit 0: I/O port 1: Timer 2 output 38C5 Group (One Time PROM version) Other function registers The RRF register (address 001216) is the 8-bit register and does not have the control function. As for the value written in this register, high-order 4 bits and loworder 4 bits interchange. It is initialized after reset. b7 RRF register (RRFR : address 001216) DB4 data storage DB5 data storage DB6 data storage DB7 data storage DB0 data storage DB1 data storage DB2 data storage DB3 data storage Fig. 50 Structure of RRF register Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 52 of 75 b0 38C5 Group (One Time PROM version) RESET CIRCUIT Poweron To reset the microcomputer, RESET pin should be held at an "L" level for 2 s or more. Then the RESET pin is returned to an "H" level (the power source voltage should be between VCC (min.) and 3.6 V, and the quartz-crystal oscillator should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage meets VIL spec. when a power source voltage passes VCC (min.). RESET VCC Power source voltage 0V Reset input voltage 0V RESET VIL spec. VCC Power source voltage detection circuit Fig. 51 Reset circuit example ROSC ........ System clock RESET Internal reset Reset address from vector table Address ? ? ? Data FFFC ADL SYNC ROSC : about 32800 cycles Notes 1: The frequency relation of f(XIN) and f() is f(ROSC) = 32 * f(). 2: The question marks (?) indicate an undefined state. Fig. 52 Reset sequence Rev.2.00 Nov 23, 2005 REJ03B0098-0200 ? page 53 of 75 FFFD ADH, ADL ADH 38C5 Group (One Time PROM version) Address Register contents Address Register contents (1) Port P0 000016 0016 (35) Timer X (low-order) 002A16 FF16 (2) Port P0 direction register 000116 0016 (36) Timer X (high-order) 002B16 FF16 (3) Port P1 000216 0016 (37) Timer X (extension) 002C16 0016 (4) Port P1 direction register 000316 0016 (38) Timer X mode register 002D16 0016 (5) Port P2 000416 0016 (39) Timer X control register 1 002E16 0016 (6) Port P2 direction register 000516 0016 (40) Timer X control register 2 002F16 0016 (7) Port P3 000616 0016 (41) Compare register 1 (low-order) 003016 0016 (8) Port P3 direction register 000716 0016 (42) Compare register 1 (high-order) 003116 0016 (9) Port P4 000816 0016 (43) Compare register 2 (low-order) 003216 0016 (10) Port P4 direction register 000916 0016 (44) Compare register 2 (high-order) 003316 0016 (11) Port P5 000A16 0016 (45) Compare register 3 (low-order) 003416 0016 (12) Port P5 direction register 000B16 0016 (46) Compare register 3 (high-order) 003516 0016 (13) Port P6 000C16 0016 (47) Timer Y (low-order) 003616 FF16 (14) Port P6 direction register 000D16 0016 (48) Timer Y (high-order) 003716 FF16 (15) Port P7 000E16 0016 (49) Timer Y mode register 003816 0016 (16) Port P7 direction register 000F16 0016 (50) Timer Y control register 003916 0016 (17) RRF register (RRFR) 001216 0016 (51) Interrupt edge selection register 003A16 0016 (18) LCD mode register 1 001316 0016 (52) CPU mode register 003B16 0 1 1 0 1 0 0 0 (19) LCD mode register 2 001416 0016 (53) Interrupt request register 1 003C16 0016 (20) AD control register 001516 0816 (54) Interrupt request register 2 003D16 0016 (21) Serial I/O1 status register 001916 1 0 0 0 0 0 0 0 (55) Interrupt control register 1 003E16 0016 (22) Serial I/O1 control register 001A16 (56) Interrupt control register 2 003F16 0016 (23) UART control register 001B16 1 1 1 0 0 0 0 0 (57) PULL register 1 0FF016 0016 (24) Serial I/O2 control register 001D16 0016 (58) PULL register 2 0FF116 0016 0FF216 0016 0016 (25) Timer 1 002016 FF16 (59) PULL register 3 (26) Timer 2 002116 0116 (60) Clock output control register 0FF316 0016 (27) Timer 3 002216 FF16 (61) Segment output disable register 0 0FF416 FF16 (28) Timer 4 002316 FF16 (62) Segment output disable register 1 0FF516 FF16 (29) PWM01 register 002416 0016 (63) Segment output disable register 2 0FF616 0F16 0FF716 0016 (30) Timer 12 mode register 002516 0016 (64) Key input control register (31) Timer 34 mode register 002616 0016 (65) Processor status register (32) Timer 1234 mode register 002716 0016 (66) Program counter (33) Timer 1234 frequency division 002816 0016 selection register (34) Watchdog timer control register 002916 0 0 1 1 1 1 1 1 Fig. 53 Internal status at reset Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 54 of 75 (PS) 1 (PCH) FFFD16 contents (PCL) FFFC16 contents X: Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. 38C5 Group (One Time PROM version) CLOCK GENERATING CIRCUIT The oscillation circuit of 38C5 group can be formed by connecting an oscillator, capacitor and resistor between XIN and XOUT (XCIN and XCOUT). To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. The clocks that are externally generated cannot be directly input to XCIN. Use the circuit constants in accordance with the oscillator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. (An external feed-back resistor may be needed depending on conditions.) However, an about 10 M external feedback resistor is needed between XCIN and XCOUT. Immediately after reset is released, only the on-chip oscillator starts oscillating, XIN -XOUT oscillation stops oscillating, and XCIN and XCOUT pins function as I/O ports. Frequency Control (1) On-chip oscillation Mode The system clock is the on-chip oscillator oscillation divided by 32. (2) Middle-speed Mode The system clock is the frequency of XIN divided by 8. (3)High-speed Mode The system clock is half the frequency of XIN. (4) Low-speed Mode The system clock is half the frequency of sub clock. After reset release and when system returns from the stop mode, the on-chip oscillator mode is selected. Refer to the clock state transition diagram for the setting of transition to each mode. The XIN-XOUT oscillation is controlled by the bit 5 of CPUM, and the sub-clock oscillation is controlled by the bit 4 of CPUM. When the mode is switched to the on-chip oscillator mode, set the bit 3 of CPUM to "1". In the on-chip oscillator mode, the oscillation by the oscillator can be stopped. In the low-speed mode, the power consumption can be reduced by stopping the XIN-XOUT oscillation. When the mode is switched from the on-chip oscillator mode to the low-speed mode, the on-chip oscillator is stopped. Set enough time for oscillation to stabilize by programming to re-start the stopped oscillation and switch the operation mode. Also, set enough time for oscillation to stabilize by programming to switch the timer count source . Notes on Clock Generating Circuit If you switch the mode between on-chip oscillator mode, middle/highspeed mode and low-speed mode, stabilize both XIN and XCIN oscillations. Especially be careful immediately after power-on and at returning from stop mode. Refer to the clock state transition diagram for the setting of transition to each mode. Set the frequency in the condition that f(XIN) > 3*f(XCIN). When the middle- and high-speed mode are not used (XIN-XOUT oscillation and external clock input are not performed), connect XIN to VCC through a resistor. Oscillation Control (1) Stop Mode If the STP instruction is executed, the system clock stops at an "H" level, and main clock and sub-clock oscillators stop. In this time, values set previously to timer 1 latch and timer 2 latch are loaded automatically to timer 1 and timer 2. Set the values to generate the wait time required for oscillation stabilization to timer 1 latch and timer 2 latch (low-order 8 bits of timer 1 and high-order 8 bits of timer 2) before the STP instruction. The frequency divider for timer 1 is used for the timer 1 count source, and the output of timer 1 is forcibly connected to timer 2. In this time, bits 0 to 5 of the timer 12 mode register are cleared to "0". The values of the timer 12 frequency divider selection register are not changed. Set the interrupt enable bits of the timer 1 and timer 2 to be disabled ("0") before executing the STP instruction. When an external interrupt is received, the clock oscillated before stop mode and the on-chip oscillator start oscillating. However, bit 3 of CPUM is set to "1" forcibly and system returns to the on-chip oscillator mode. Oscillator restarts when reset occurs or an interrupt request is received, but the system clock is not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize. (2) Wait Mode If the WIT instruction is executed, only the system clock stops at an "H" state. The states of main clock, on-chip oscillator and sub clock are the same as the state before executing the WIT instruction, and oscillation does not stop. Since supply of system clock is started immediately after the interrupt is received, the instruction can be executed immediately. XCIN XCOUT Rf CCIN XIN Rd (Note) Rd CCOUT CIN Fig. 54 Ceramic resonator circuit example XCIN XCOUT Rf XIN XOUT Open Rd External oscillation circuit CCOUT VCC VSS Fig. 55 External clock input circuit page 55 of 75 COUT Notes : Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feedback resistor between XIN and XOUT following the instruction. CCIN Rev.2.00 Nov 23, 2005 REJ03B0098-0200 XOUT 38C5 Group (One Time PROM version) On-chip oscillator 1/4 XIN XOUT (Note 2) Main clock selection bit "1" CPUM BIT3 "0" XIN-XOUT oscillation stop bit CPUM BIT5 XCOUT XCIN "0" Internal system clock selection bit CPUM BIT7 (Note 1) "01" "1" Port Xc switch bit CPUM BIT4 Timer 2 count source selection bits Timer 1 Frequency divider for Timer "0" "1" Timer 1 count source selection bits "00" Timer 2 "00" "10" 1/2 1/4 "1" Main clock division ratio selection bit CPUM BIT6 "0" "0" "1" Main clock selection bit CPUM BIT3 Internal system "0" clock selection bit CPUM BIT7 "1" System clock Q S R S STP instruction WIT instruction R Q Q S R STP instruction Reset Interrupt disable flag I Interrupt request Notes 1: When the XCIN-XCOUT oscillation is selected as the system clock, set the port Xc switch bit to "1". 2: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions. Fig. 56 Clock generating circuit block diagram Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 56 of 75 38C5 Group (One Time PROM version) Reset release On-chip oscillator mode XIN stop XCIN stop = f(ROSC)/32 CM7=0 CM6=1 (Note 5) CM5=1 CM4=0 CM3=1 C M4 Low-speed mode XIN stop XCIN oscillation = f(ROSC)/32 CM7=0 CM6=1 (Note 5) CM5=1 CM4=1 CM3=1 XIN stop XCIN oscillation = 16 kHz CM7=1 CM6=1 CM5=1 CM4=1 CM3=* (Note 9) C M7 C M6 C M4 C M5 C M5 XIN oscillation XCIN stop = f(ROSC)/32 CM7=0 CM6=1 (Note 5) CM5=0 CM4=0 CM3=1 C M4 CM5 C M5 XIN oscillation XCIN oscillation = f(ROSC)/32 CM7=0 CM6=1 (Note 5) CM5=0 CM4=1 CM3=1 CM3 CM3 XIN oscillation XCIN oscillation = 16 kHz CM7=1 CM6=1 CM5=0 CM4=1 CM3=* (Note 9) C M7 CM7 CM5 CM6 XIN oscillation XCIN oscillation = 16 kHz CM7=1 CM6=0 (Note 5) CM5=0 CM4=1 CM3=* (Note 9) C M7 Middle-speed mode XIN oscillation XCIN stop = 1 MHz CM7=0 CM6=1 CM5=0 CM4=0 CM3=0 CM4 XIN oscillation XCIN oscillation = 1 MHz CM7=0 CM6=1 CM5=0 CM4=1 CM3=0 b7 C M6 C M6 b3 CPU mode register (CPUM : address 003B16) High-speed mode XIN oscillation XCIN stop = 4 MHz CM7=0 CM6=0 (Note 5) CM5=0 CM4=0 CM3=0 C M4 XIN oscillation XCIN oscillation = 4 MHz CM7=0 CM6=0 (Note 5) CM5=0 CM4=1 CM3=0 Main clock selection bit 0: Ceramic oscillation 1: On-chip oscillator Port Xc switch bit 0: I/O port function (oscillation stop) 1: XCIN-XCOUT oscillation function XIN-XOUT oscillation stop bit 0: Oscillation 1: Stop Main clock division ratio selection bit 0: f(XIN)/2 (high-speed mode) 1: f(XIN)/8 (low-speed mode) Internal system clock selection bit 0: Main clock selected (middle-speed/high-speed/on-chip oscillator mode) 1: XCIN-XCOUT selected (low-speed mode) Notes 1: Switch the mode by the arrows shown between the mode blocks. The all modes can be switched to the stop mode or the wait mode. 2: Timer and LCD operate in the wait mode. System is returned to the source mode when the wait mode is ended. 3: CM4, CM5 and CM6 are retained in the stop mode. System is returned to the on-chip oscillator mode (CM3=1, CM7=0). 4: When the stop mode is ended, set the oscillation stabilizing wait time in the on-chip oscillator mode. 5: When the stop mode is ended, set the initial value to CM6 (CM6=1). 6: Execute the transition after the oscillation used in the destination mode is stabilized. 7: When system goes to on-chip oscillator mode, the oscillation stabilizing wait time is not needed. 8: Do not go to the high-speed mode from the on-chip oscillator mode. 9: Write the proper values for destination mode beforehand. 10: The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. f(ROSC) indicates the oscillation frequency of on-chip oscillator. Fig. 57 State transitions of system clock Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 57 of 75 38C5 Group (One Time PROM version) PROM Mode M38C59GFFP/HP (referred to as "the MCU") has a PROM Mode as well as the normal operation mode. PROM Mode enables an external device (referred to as "Programmer") to read and program the built-in EPROM via a minimum number of serial I/O pins by sending commands to control the MCU. There are three operation modes in PROM Mode : Read, Program and Program-Verify. Three commands are defined to enable each mode respectively. The format of the serial I/O is : clock synchronous and LSB-datafirst. P20/SEG0/(KW4) P21/SEG1/(KW5) P22/SEG2/(KW6) P23/SEG3/(KW7) P24/SEG4 P25/SEG5 P26/SEG6 P27/SEG7 P00/SEG8 P01/SEG9 P02/SEG10 P03/SEG11 P04/SEG12 P05/SEG13 P06/SEG14 P07/SEG15 P10/SEG16 P11/SEG17 P12/SEG18 P13/SEG19 P14/SEG20 P15/SEG21 P16/SEG22 P17/SEG23 To enable PROM Mode, use the pin connection shown in Figure 58 to 59 and apply power (VCC). Then execute the new One Time PROM entry operation, called "Mad Dog Entry". 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P47/SRDY2/(KW3) P46/SCLK2/(KW2) P45/SOUT2/(KW1) P44/SIN2/(KW0) P43/SRDY1 P42/SCLK1 P41/TXD P40/RXD AVss VREF P57/AN7/ADKEY0 P56/AN6 P55/AN5 P54/AN4 P53/AN3 P52/AN2 65 66 67 68 69 40 39 38 70 71 72 73 74 75 76 77 M38C59GFFP M3822xMX-XXXFP 30 29 28 27 26 25 78 79 80 P51/AN1/RTP1 P50/AN0/RTP0 P67/CNTR1/(LED5) P66/INT10/CNTR0/(LED4) P65/TXOUT1 /(LED3) P64/INT2 /(LED2) P63/TXOUT2/(LED1) P62/INT00 /(LED0) VPP CNVSS RESET RESETB P61/XCOUT P60/XCIN VSS VSS XIN XIN XOUT XOUT VCC VCC ESDA P74/PWM1/T4OUT ESPGMB P73/PWM0/T3OUT P72/T2OUT/CKOUT ESCLK VL3 VL2 P71/C2/INT11 P70/C1/INT01 VL1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Fig. 58 Pin diagram in PROM mode (PLQP0080GA-A package type) Rev.2.00 Nov 23, 2005 REJ03B0098-0200 37 36 35 34 33 32 31 page 58 of 75 P30/SEG24 P31/SEG25 P32/SEG26 P33/SEG27 P34/SEG28 P35/SEG29 P36/SEG30 P37/SEG31 COM7/SEG32 COM6/SEG33 COM5/SEG34 COM4/SEG35 COM3 COM2 COM1 COM0 42 41 44 43 52 51 50 49 48 47 46 45 54 53 40 39 38 37 36 35 34 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 33 32 31 30 29 28 27 26 25 24 23 22 M38C59GFHP 21 19 20 18 17 15 16 12 13 14 10 11 8 9 7 4 5 6 3 P67/CNTR1/(LED5) P66/INT10/CNTR0 /(LED4) P65/TXOUT1 /(LED3) P64/INT2 /(LED2) P63/TXOUT2/(LED1) P62/INT00/(LED0) VPP CNVSS RESETB RESET P61/XCOUT P60/XCIN VSS VSS XIN XIN XOUT XOUT VCC VCC ESDA P74/PWM1/T4OUT ESPGMB P73/PWM0/T3OUT ESCLK P72/T2OUT/CKOUT VL3 VL2 P71/C2/INT11 2 80 1 P21/SEG1/(KW5) P20/SEG0/(KW4) P47/SRDY2/(KW3) P46/SCLK2/(KW2) P45/SOUT2/(KW1) P44/SIN2/(KW0) P43/SRDY1 P42/SCLK1 P41/TXD P40/RXD AVss VREF P57/AN7/ADKEY0 P56/AN10 P55/AN5 P54/AN4 P53/AN3 P52/AN2 P51/AN1/RTP1 P50/AN0/RTP0 55 60 59 58 57 56 P22/SEG2/(KW6) P23/SEG3/(KW7) P24/SEG4 P25/SEG5 P26/SEG6 P27/SEG7 P00/SEG8 P01/SEG9 P02/SEG10 P03/SEG11 P04/SEG12 P05/SEG13 P06/SEG14 P07/SEG15 P10/SEG16 P11/SEG17 P12/SEG18 P13/SEG19 P14/SEG20 P15/SEG21 38C5 Group (One Time PROM version) Fig. 59 Pin Diagram in PROM mode (PLQP0080KB-A package type) Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 59 of 75 P16/SEG22 P17/SEG23 P30/SEG24 P31/SEG25 P32/SEG26 P33/SEG27 P34/SEG28 P35/SEG29 P36/SEG30 P37/SEG31 COM7/SEG32 COM6/SEG33 COM5/SEG34 COM4/SEG35 COM3 COM2 COM1 COM0 VL1 P70/C1/INT01 38C5 Group (One Time PROM version) Precaution for Handling One-Time-Programmable Devices Our company ships one-time-programmable version MCUs (OneTime PROM MCU) without being screened by the PROM writing test. To ensure the reliability of the MCU, We recommend that the user performs the program and test procedure shown in Figure 60 before using the MCU. Programming with PROM programmer Screening (Caution) (150 C for 40 hours) Verification with PROM programmer Functional check in target device Caution: The screening temperature is far higher than the storage temperature. Never expose to 150 C exceeding 100 hours. Fig. 60 Programming and testing of One Time PROM Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 60 of 75 38C5 Group (One Time PROM version) ROM Code Access Protection We would like to support a simple ROM code protection function that prevents a party other than the ROM-code owner to read and reprogram the builit-in PROM code of the MCU. The MCU has 7 bytes of dedicated ROM spaces in address 0xFFD4 to 0xFFDA, as an ID-code (referred to as "the ID-code") enabling a Programmer to verify with the input ID-code and validate further operations. Expected Programmer ID-Code Verification Function First, Programmer must check the ID-code of the MCU. If the ID-code is still in blank, Programmer enebles all operations, Read, Program, and Program-Verify. When Programmer programs the MCU, Programmer also programs the given ID-code as well as the actual firmware. If the ID-code is not blank, Programmer verifies it with the input IDcode. When the ID-codes don't mutch, Programmer will reject all further operations. If they match, Programmer perform operations according to the given command. Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 61 of 75 Address FFD416 FFD516 FFD616 FFD716 FFD816 FFD916 FFDA16 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Fig. 61 ROM-Code Protection ID Location 38C5 Group (One Time PROM version) NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1." After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Serial Interface In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to "1." Serial I/O continues to output the final bit from the TXD pin after transmission is completed. A/D Converter Interrupts The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. Decimal Calculations * To calculate in decimal notation, set the decimal mode flag (D) to "1," then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing an SEC, CLC, or CLD instruction. * In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers * If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). * The timers share the one frequency divider to generate the count source. Accordingly, when each timer starts operating, initializing the frequency divider is not executed. Therefore, when the frequency divider is selected for the count source, the delay of the maximum one cycle of the count source is generated until the timer starts counting or the waveform is output from timer starts operating. Also, the count source cannot be checked externally. Multiplication and Division Instructions * The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. * The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used: * The data transfer instruction (LDA, etc.) * The operation instruction when the index X mode flag (T) is "1" * The addressing mode which uses the value of a direction register as an index * The bit-test instruction (BBC or BBS, etc.) to a direction register * The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 62 of 75 The comparator is constructed linked to a capacitor. The conversion accuracy may be low because the change is lost if the conversion speed is not enough. Accordingly, set f(XIN) to at least 500 kHz during A/D conversion in the middle- or high- speed mode. Also, do not execute the STP and WIT instructions during the A/D conversion. In the low-speed mode, since the A/D conversion is executed by the built-in self-oscillation circuit, the minimum value of f(XIN) frequency. Instruction Execution Time The instruction execution time is obtained by multiplying the number of cycles shown in the list of machine instructions by the period of the internal clock . 38C5 Group (One Time PROM version) NOTES ON USE VL3 pin When LCD drive control circuit is not used, connect VL3 to VCC. Noise Countermeasures against noise The following countermeasures are effective against noise in theory, however, it is necessary not only to take masures as follows but to evaluate before actual use. XIN XOUT VSS (1) Shortest wiring length Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20 mm). Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise Reset circuit RESET VSS VSS N.G. Reset circuit VSS RESET VSS O.K. Fig. 62 Wiring for the RESET pin Wiring for clock input/output pins * Make the length of wiring which is connected to clock I/O pins as short as possible. * Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. * Separate the VSS pattern only for oscillation from other VSS patterns. Reason If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 63 of 75 N.G. XIN XOUT VSS O.K. Fig. 63 Wiring for clock I/O pins (2) Connection of bypass capacitor across VSS line and VCC line Connect an approximately 0.1 F bypass capacitor across the VSS line and the VCC line as follows: * Connect a bypass capacitor across the VSS pin and the VCC pin at equal length. * Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. * Use lines with a larger diameter than other signal lines for VSS line and VCC line. * Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. AA AA AA AA AA VCC VSS N.G. AA AA AA AA AA VCC VSS O.K. Fig. 64 Bypass capacitor across the VSS line and the VCC line 38C5 Group (One Time PROM version) (3) Oscillator concerns In order to obtain the stabilized operation clock on the user system and its condition, contact the oscillator manufacturer and select the osillator and oscillation circuit constants. Be careful especially when range of voltage and temperature is wide. Also, take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (5) Difference of memory type and size When Mask ROM and PROM version and memory size differ in one group, actual values such as an electrical characteristics, A/D conversion accuracy, and the amount of -proof of noise incorrect operation may differ from the ideal values. When these products are used switching, perform system evaluation for each product of every after confirming product specification. Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. (6) Wiring to VPP pin of One Time PROM version Connect an approximately 5 k resistor to the VPP pin at the shortest possible in series and also to the VSS pin. Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. Reason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. Note: Even when a circuit which included an approximately 5 k resistor is used in the Mask ROM version, the microcomputer operates correctly. Reason The VPP pin of the One Time PROM version is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the VPP pin is low to allow the electric current for writing flow into the built-in PROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal instruction codes or data are read from the built-in PROM, which may cause a program runaway. The shortest P40/(VPP) (Note) Approx. 5k VSS (Note) The shortest Keeping oscillator away from large current signal lines Microcomputer Note. Shows the microcomputer's pin. Mutual inductance M Fig. 66 Wiring for the VPP pin of One Time PROM XIN XOUT VSS Large current GND Installing oscillator away from signal lines where potential levels change frequently N. Do not crossG. CNTR XIN XOUT VSS Fig. 65 Wiring for a large current signal line/Writing of signal lines where potential levels change frequently (4) Analog input The analog input pin is connected to the capacitor of a voltage comparator. Accordingly, sufficient accuracy may not be obtained by the charge/discharge current at the time of A/D conversion when the analog signal source of high-impedance is connected to an analog input pin. In order to obtain the A/D covnversion result stabilized more, please lower the impedance of an analog signal source, or add the smoothing capacitor to an analog input pin. Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 64 of 75 Electric Characteristic Differences Between Mask ROM and One Time PROM Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between the mask ROM and One Time PROM version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with the One Time PROM version and then switching to use of the mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version. Oscillation Circuit Constant (1) Determine an oscillation circuit constant after consulting the oscillator manufacturer about the matching characteristic evaluation. (2) Since oscillation circuit constants may be differences between the One Time PROM version and the mask ROM version, evaluate them, respectively. Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. 38C5 Group (One Time PROM version) ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Table 12 Absolute maximum ratings Symbol VCC VI VI VI VI VI VI VO VO VO VO VO VO Pd Topr Tstg Parameter Power source voltage Input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P74 Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage C1, C2 Input voltage RESET, XIN Output voltage C1, C2 Output voltage P00-P07, P10-P17, P20-P27, P30-P37 Output voltage P40-P47, P50-P57, P60-P67, P72-P74 Output voltage VL3 Output voltage VL2, SEG32-SEG35 Output voltage XOUT Power dissipation Operating temperature Storage temperature Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 65 of 75 Conditions All voltages are based on Vss. When an input voltage is measured, output transistors are cut off. Ratings -0.3 to 4.0 -0.3 to VCC+0.3 Unit V V V V V V V V V At output port At segment output -0.3 to VL2 VL1 to VL3 VL2 to 6.5 -0.3 to 6.5 -0.3 to VCC+0.3 -0.3 to 6.5 -0.3 to VCC -0.3 to VL3 -0.3 to VCC+0.3 -0.3 to 6.5 -0.3 to VL3 -0.3 to VCC + 0.3 300 -20 to 85 -40 to 125 Ta = 25C V V V V mW C C 38C5 Group (One Time PROM version) Recommended Operating Conditions Table 13 Recommended operating conditions (Vcc = 1.8 to 3.6 V, Ta = -20 to 85C, unless otherwise noted) Symbol Parameter VCC Power source voltage (Note 1) VSS VLI VREF AVSS VIA VIH Power source voltage VL1 input voltage Voltage multiplier is used A/D converter reference voltage Analog power source voltage Analog input voltage AN0-AN7 "H" input voltage P00-P07, P10-P17, P24-P27, P30-P37, P41, P43, P50-P57, P60(CM4=0), P61, P65, P72-P74 "H" input voltage P20-P23, P40, P42, P44-P47, P62-P64, P66-P67, P70, P71 "H" input voltage RESET "H" input voltage XIN "L" input voltage P00-P07, P10-P17, P24-P27, P30-P37, P41, P43, P50-P57, P60(CM4=0), P61, P65, P72-P74 "L" input voltage P20-P23, P40, P42, P44-P47, P62-P64, P66-P67, P70, P71 "L" input voltage RESET "L" input voltage XIN VIH VIH VIH VIL VIL VIL VIL High-speed mode f(XIN) = 6 MHz f(XIN) = 4 MHz Middle-speed mode f(XIN) = 12.5 MHz f(XIN) = 8 MHz f(XIN) = 6 MHz Low-speed mode Oscillation start voltage (Note 2) Min. 3.0 2.0 3.0 2.0 1.8 1.8 0.15 f + 1.3 Limits Typ. 3.3 3.3 3.3 3.3 3.3 3.3 Max. 3.6 3.6 3.6 3.6 3.6 3.6 AVSS 0.7VCC VCC VCC V V V V V V V V V V V V V 0.8VCC VCC V 0.8VCC 0.8VCC 0 VCC VCC 0.3VCC V V V 0 0.2VCC V 0 0 0.2VCC 0.2VCC V V 1.3 2.0 0 1.8 2.1 VCC 0 Notes 1: When the A/D converter is used, refer to the recommended operating conditions of the A/D converter. 2: The oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or temperature, etc. When power supply voltage is low and the high frequency oscillator is used, an oscillation start will require sufficient conditions. f: Oscillation frequency (MHz) of oscillator. When the 8 MHz oscillation is used, assign "8" to "f". Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 66 of 75 Unit 38C5 Group (One Time PROM version) Table 14 Recommended operating conditions (Mask ROM version) (Vcc = 1.8 to 3.6 V, Ta = -20 to 85C, unless otherwise noted) Symbol IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOL(avg) IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOL(avg) Parameter "H" total peak output current (Note 1) P00-P07, P10-P17, P20-P27, P30-P37, P72-P74 "H" total peak output current (Note 1) P40-P47, P50-P57, P60-P67 "L" total peak output current (Note 1) P00-P07, P10-P17, P20-P27, P30-P37, P72-P74 "L" total peak output current (Note 1) P40-P47, P50-P57, P60, P61 "L" total peak output current (Note 1) P62-P67 "H" total average output current (Note 1) P00-P07, P10-P17, P20-P27, P30-P37, P72-P74 "H" total average output current (Note 1) P40-P47, P50-P57, P60-P67 "L" total average output current (Note 1) P00-P07, P10-P17, P20-P27, P30-P37, P72-P74 "L" total average output current (Note 1) P40-P47, P50-P57, P60, P61 "L" total average output current (Note 1) P62-P67 "H" peak output current (Note 2) P00-P07, P10-P17, P20-P27, P30-P37 "H" peak output current (Note 2) P40-P47, P50-P57, P60-P67, P72-P74 "L" peak output current (Note 2) P00-P07, P10-P17, P20-P27, P30-P37 "L" peak output current (Note 2) P40-P47, P50-P57, P60, P61, P72-P74 "L" peak output current (Note 2) P62-P67 "H" average output current (Note 3) P00-P07, P10-P17, P20-P27, P30-P37 "H" average output current (Note 3) P40-P47, P50-P57, P60-P67, P72-P74 "L" average output current (Note 3) P00-P07, P10-P17, P20-P27, P30-P37 "L" average output current (Note 3) P40-P47, P50-P57, P60, P61, P72-P74 "L" average output current (Note 3) P62-P67 Min. Limits Typ. Max. -40 Unit mA -40 mA 40 mA 40 mA 110 mA -20 mA -20 mA 20 mA 20 mA 90 mA -2 mA -5 mA 5.0 mA 10 mA 30 mA -1.0 mA -2.5 mA 2.5 mA 5.0 mA 15 mA Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current is average value measured over 100 ms. Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 67 of 75 38C5 Group (One Time PROM version) Table 15 Recommended operating conditions (Vcc = 1.8 to 3.6 V, Ta = -20 to 85C, unless otherwise noted) Symbol Parameter f(CNTR0) Timer X and Timer Y f(CNTR1) Input frequency (duty cycle 50%) Main clock input frequency f(XIN) (duty cycle 50%) (Note 1) f(XCIN) Sub-clock oscillation frequency (duty cycle 50%) (Notes 2, 4) Min. Limits Typ. (2.0 V VCC < 3.6 V) (VCC < 2.0 V) High-speed mode (2.0 V < VCC 3.6 V) Middle-speed mode (Notes 3, 4) (3.0 V VCC 3.6 V) Middle-speed mode (Notes 3, 4) (2.0 V VCC 3.6 V) Middle-speed mode (Notes 3, 4) 32.768 Unit Max. VCC 5VCC-8 12.5 MHz MHz MHz 12.5 MHz 8.0 MHz 6.0 80 MHz kHz Notes 1: When the A/D converter is used, refer to the recommended operationg conditions of the A/D converter. 2: When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. 3: When the timer X dividing frequency selection bit and timer Y dividing frequency selection bit are "01(1/1 SOURCE)" or "10(1/2 SOURCE)", the limits at the high-speed mode are suitable for the recommended operating condition of main clock input frequency f(XIN). 4: The oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or temperature, etc. When power supply voltage is low and the high frequency oscillator is used, an oscillation start will require sufficient conditions. Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 68 of 75 38C5 Group (One Time PROM version) Electrical Characteristics Table 16 Electrical characteristics (Vcc = 3.0 to 3.6 V, Ta = -20 to 85C, unless otherwise noted) Parameter Symbol VOH VOH VOL VOL VOL VT+-VT- VT+-VTVT+-VTIIH IIH IIH IIH IIL IIL IIL IIL ROSC "H" output voltage P00-P07, P10-P17, P20-P27, P30-P37 Test conditions IOH = -0.6 mA VCC = 2.5 V "H" output voltage IOH = -1.25 mA P40-P47, P50-P57, P60-P67, P72-P74 (Note) IOH = -1.25 mA VCC = 2.5 V "L" output voltage IOL = 1.25 mA P00-P07, P10-P17, P20-P27, P30-P37 IOL = 1.25 mA VCC = 2.5 V "L" output voltage IOL = 2.5 mA P40-P47, P50-P57, P60, P61, P72-P74 (Note) IOL = 2.5 mA VCC = 2.5 V "L" output voltage IOL = 3.0 mA P62-P67 VCC = 2.5 V Hysteresis INT00, INT01, INT10, INT11, INT2, CNTR0, CNTR1, KW0-KW7 Hysteresis SIN2, SCLK1, SCLK2, RxD Hysteresis RESET VCC = 2.0 - 3.6 V on RESET "H" input current VI = VCC P00-P07, P10-P17, P20-P27, P30-P37 "H" input current VI = VCC P40-P47, P50-P57, P60-P67, P70-P74 "H" input current RESET VI = VCC "H" input current XIN VI = VCC "L" input current VI = VSS P00-P07, P10-P17, P20-P27, P30-P37 Pull-up "OFF" VCC = 3.0 V, VI = VSS Pull-up "ON" "L" input current VI = VSS P40-P47, P50-P57, P60-P67, P72-P74 Pull-up "OFF" VCC = 3.0 V, VI = VSS Pull-up "ON" "L" input current RESET VI = VSS "L" input current XIN VI = VSS On-chip oscillator frequency VCC = 3.3 V, Ta = 25 C Limits Min. Typ. page 69 of 75 Unit VCC-1.0 V VCC-0.5 VCC-1.0 V V 0.5 1.0 V V 0.5 1.0 V V 0.8 V 0.3 V 0.3 0.3 5.0 V V A 5.0 A 5.0 -5.0 A A A -100 A -5.0 A -45 A -5.0 A A kHz 4.0 -25 -50 -6.5 -25 1300 -4.0 2700 Note: When the port Xc switch bit (bit 4 of address 003B16) of CPU mode register is "1", the drivability of P61 is different from the above. Rev.2.00 Nov 23, 2005 REJ03B0098-0200 Max. 4000 38C5 Group (One Time PROM version) Table 17 Electrical characteristics (Vcc = 1.8 to 3.6 V, Ta = -20 to 85C, f(XCIN) = 32.768 kHz, output transistors in the cut-off state, AD converter stopped, unless otherwise noted) Limits Symbol Parameter Test conditions Unit Min. Typ. Max. VRAM RAM hold voltage When clock is stopped 1.8 3.6 V ICC Power source 0.6 1.2 mA High-speed mode Vcc = 2.5 V f(XIN) = 4 MHz current 0.3 0.6 mA f(XIN) = 4 MHz (in WIT state) 0.4 0.8 mA f(XIN) = 2 MHz 0.5 1.0 mA Middle-speed mode Vcc = 2.5 V f(XIN) = 8 MHz 0.3 0.6 mA f(XIN) = 8 MHz (in WIT state) 0.3 0.6 mA f(XIN) = 4 MHz 7.0 14 A Low-speed mode Vcc = 2.5 V f(XIN) = stop 3.5 7.0 A in WIT state 35 90 A On-chip oscillator mode VCC = 2.5 V 25 75 A f(XIN) and, f(XCIN) = stopped VCC = 2.5 V (in WIT state) 0.1 1.0 A All oscillations stopped Ta = 25 C 10 A (in STP state) Ta = 85 C 0.4 mA Current increased f(XIN) = 6 MHz, VCC = 3.3 V at A/D converter operating Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 70 of 75 in middle- or high-speed mode f(XIN) = stop, VCC = 3.3 V in on-chip oscillator operating f(XIN) = stop, VCC = 3.3 V in low-speed mode 0.1 mA 0.1 mA 38C5 Group (One Time PROM version) A/D Converter Characteristics Table 18 A/D converter recommended operating condition (Vcc = 2.0 to 3.6 V, Ta = -20 to 85C, output transistors in cut-off state, unless otherwise noted) Symbol VCC VIH VIL f(XIN) Parameter Power source voltage "H" input voltage ADKEY0 "L" input voltage ADKEY0 AD converter control clock (Note) (Low-speed * on-chip oscillator mode excluded) Test conditions Min. 2.0 0.9Vcc 0 Limits Typ. VCC 2.2 V 2.2 V < VCC 3.0 V 3.0 V < VCC 3.6 V Unit Max. 3.6 V Vcc V 0.7 VCC-0.5 V 20 Vcc-38 MHz 45 Vcc-35 MHz 8 12.5 MHz Note: Confirm the recommended opearting condition for main clock input frequency. Table 19 A/D converter characteristics (Vcc = 2.0 to 3.6 V, Ta = -20 to 85C, output transistors in cut-off state, low-speed * on-chip oscillator mode included, unless otherwise noted) Symbol Parameter -- ABS Resolution Absolute accuracy (quantification error excluded) Tconv Conversion time RLADDER IVREF IIA Ladder resistor Reference input current Analog input current Test conditions Min. Limits Typ. 2.5 < VCC 3.6, f(XIN) 6 MHz AD conversion clock = SOURCE/2 10bitAD mode 2.2 < VCC 2.5, f(XIN) 12.5 MHz or Low-speed mode * on-chip oscillator mode AD conversion clock = SOURCE/2 10bitAD mode 3.0 < VCC 3.6, f(XIN) 12.5 MHz AD conversion clock = SOURCE/8 8bitAD mode 2.2 < VCC 3.0, f(XIN) 8 MHz AD conversion clock = SOURCE/8 8bitAD mode 2.0 < VCC 2.2, f(XIN) 6 MHz AD conversion clock = SOURCE/8 or Low-speed mode * on-chip oscillator mode AD conversion clock = SOURCE/2 8bitAD mode AD conversion clock = SOURCE/2 10bitAD mode VREF = 3.3 V Max. 10 4 Unit Bits LSB 4 2 2 12 30 35 100 tc(AD)121 (Note) 100 130 5.0 s k A A Note: When "SOURCE/8" is selected by the AD conversion clock selection bit, the above conversion time is multiplied by 4. The operation clock is XIN in the middle- or high-speed mode, or the on-chip oscillator in the other modes. When the A/D conversion is executed in the middle- or high-speed mode, set f(XIN) 500 kHz. tc(AD): One cycle of control clock for A/D converter. XIN input is used in the middel- or high-speed mode, and on-chip oscillator is used in the low- or on-chip oscillator mode for the control clock. Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 71 of 75 38C5 Group (One Time PROM version) Timing Requirements And Switching Characteristics Table 20 Timing requirements (Vcc = 1.8 to 3.6 V, Vss = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol Limits Parameter tw(RESET) tc(XIN) Reset input "L" pulse width Main clock input cycle time (XIN input) twH(XIN) Main clock input "H" pulse width twL(XIN) Main clock input "L" pulse width tc(CNTR) CNTR0, CNTR1 input cycle time twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1) twH(SCLK1) twL(SCLK1) tsu(RxD-SCLK1) th(SCLK1-RxD) tc(SCLK2) twH(SCLK2) twL(SCLK2) tsu(RxD-SCLK2) th(SCLK2-RxD) CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT00, INT01, INT10, INT11, INT2 input "H" pulse width INT00, INT01, INT10, INT11, INT2 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input "H" pulse width (Note) Serial I/O1 clock input "L" pulse width (Note) Serial I/O1 input setup time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input setup time Serial I/O2 input hold time (2.0 V < VCC 3.6 V) (VCC 2.0 V) (2.0 V < VCC 3.6 V) (VCC 2.0 V) (2.0 V < VCC 3.6 V) (VCC 2.0 V) (2.0 V < VCC 3.6 V) (VCC 2.0 V) Note : When bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when bit 6 of address 001A16 is "0" (UART). Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 72 of 75 Min. 2 125 166 50 70 50 70 1000/Vcc 1000/(5Vcc-8) tc(CNTR)/2-20 tc(CNTR)/2-20 230 230 2000 950 950 400 200 2000 950 950 400 200 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 38C5 Group (One Time PROM version) Table 21 Switching characteristics (Vcc = 1.8 to 3.6 V, Vss = 0 V, Ta = -20 to 85C, unless otherwise noted) twH(SCLK1) twL(SCLK1) td(SCLK1-TxD) tV(SCLK1-TxD) tr(SCLK1) tf(SCLK1) twH(SCLK2) twL(SCLK2) tf(SCLK2) td(SCLK2-SOUT2) tV(SCLK2-SOUT2) Limits Parameter Symbol Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 clock output falling time Serial I/O2 output delay time Serial I/O2 output valid time Min. Typ. Max. tc(SCLK1)/2-80 tc(SCLK1)/2-80 (Note) (Note) 350 -30 80 80 tc(SCLK1)/2-80 tc(SCLK1)/2-80 80 350 -30 Note: The P41/TxD P-channel output disable bit (bit 4 of address 001B16) of UART control register is "0." 1k Measurement output pin Measurement output pin 100pF 100pF CMOS output N-channel open-drain output (Note) Note: When bit 4 of the UART control register (address 001B16) is " 1." (N-channel open-drain output mode) Fig. 67 Circuit for measuring output switching characteristics Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 73 of 75 Unit ns ns ns ns ns ns ns ns ns ns ns 38C5 Group (One Time PROM version) tC(CNTR) tWL(CNTR) tWH(CNTR) 0.8VCC CNTR0, CNTR1 0.2VCC tWL(INT) tWH(INT) INT00,INT01 INT10,INT11 INT2 0.8VCC 0.2VCC tW(RESET) RESET 0.8VCC 0.2VCC tC(XIN) tWL(XIN) tWH(XIN) 0.8VCC XIN tf SCLK1 SCLK2 0.2VCC tC(SCLK1), tC(SCLK2) tr tWL(SCLK1), tWL(SCLK2) 0.8VCC 0.2VCC tsu(RXD-SCLK1), tsu(SIN2-SCLK2) RXD SIN2 th(SCLK1-RXD), th(SCLK2-SIN2) 0.8VCC 0.2VCC td(SCLK1-TXD),td(SCLK2-SOUT2) TXD SOUT2 Fig. 68 Timing chart Rev.2.00 Nov 23, 2005 REJ03B0098-0200 tWH(SCLK1), tWH(SCLK2) page 74 of 75 tv(SCLK1-TXD), tv(SCLK2-SOUT2) 38C5 Group (One Time PROM version) PACKAGE OUTLINE JEITA Package Code P-LQFP80-14x20-0.80 RENESAS Code PLQP0080GA-A Previous Code 80P6U-A MASS[Typ.] 1.0g HD *1 D 41 64 65 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 40 bp c HE *2 E c1 b1 Reference Symbol ZE Terminal cross section 80 25 1 24 Index mark ZD y *3 e JEITA Package Code P-LQFP80-12x12-0.50 RENESAS Code PLQP0080KB-A c A1 L A2 A F bp L1 x Previous Code 80P6Q-A Detail F D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Dimension in Millimeters Min Nom Max 19.9 20.0 20.1 13.9 14.0 14.1 1.4 21.8 22.0 22.2 15.8 16.0 16.2 1.7 0.05 0.125 0.2 0.32 0.37 0.42 0.35 0.09 0.145 0.20 0.125 0 8 0.8 0.20 0.10 0.8 1.0 0.3 0.5 0.7 1.0 MASS[Typ.] 0.5g HD *1 D 60 41 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 40 61 bp E c *2 HE c1 b1 Reference Symbol ZE Terminal cross section 80 21 1 20 ZD Index mark bp c A *3 A1 y e A2 F L x L1 Detail F Rev.2.00 Nov 23, 2005 REJ03B0098-0200 page 75 of 75 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Dimension in Millimeters Min Nom Max 11.9 12.0 12.1 11.9 12.0 12.1 1.4 13.8 14.0 14.2 13.8 14.0 14.2 1.7 0.1 0.2 0 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0 10 0.5 0.08 0.08 1.25 1.25 0.3 0.5 0.7 1.0 REVISION HISTORY Rev. Date Description Summary Page 1.00 Mar. 31, 2004 - 38C5 Group Data Sheet First edition issued 1.10 Jun.14.2004 All pages Words standardized: On-chip oscillator, A/D converter 2.00 Nov. 23, 2005 2, 3, 7, 8 14 44 46 50 55 58, 59 64 65 75 Package name revised. Fig.11: Memory map of special function register (SFR) Note added. Table 9: Maximum number of display pixels at each duty ratio revised. Voltage Multiplier revised. Table 10: Bias control and applied voltage to VL1-VL3 revised. Fig.42: Example of circuit at each bias revised. Standard Operation of Watchdog Timer revied. Bit 6 of Watchdog Timer Control Register revised. Fig.47: Structure of Watchdog timer control register revised. Fig.54: Ceramic resonator circuit example revised. Package name revised. Fig.66: Wiring for the VPP pin of One Time PROM revised. Power Source Voltage added. Table 12: absolute maximum ratings revised. PACKAGE OUTLINE revised. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> 2-796-3115, Fax: <82> 2-796-2145 Renesas Technology Malaysia Sdn. Bhd. Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 (c) 2005. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .4.0